kicad-source/common/drc_rules.keywords
Seth Hillbrand de8c4d4b01 ADDED: via_dangling constraint
Allows programmatic suppression of this error if you don't care about it

Fixes https://gitlab.com/kicad/code/kicad/-/issues/18058
2025-09-02 08:26:18 -07:00

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annular_width
assertion
assign_component_class
board_edge
buried_via
clearance
condition
connection_width
constraint
courtyard_clearance
creepage
diff_pair_gap
diff_pair_uncoupled
disallow
edge_clearance
error
exclusion
footprint
graphic
hole
hole_clearance
hole_size
hole_to_hole
ignore
inner
layer
length
max
mechanical_clearance
mechanical_hole_clearance
micro_via
min
min_resolved_spokes
none
npth
opt
outer
pad
pth
physical_clearance
physical_hole_clearance
rule
severity
silk_clearance
skew
solder_mask_expansion
solder_paste_abs_margin
solder_paste_rel_margin
solid
text
text_height
text_thickness
thermal_reliefs
thermal_relief_gap
thermal_spoke_width
track
track_angle
track_width
track_segment_length
version
via
via_count
via_dangling
via_diameter
warning
within_diff_pairs
zone
zone_connection