mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-13 17:53:11 +02:00
ADDED: via_dangling constraint
Allows programmatic suppression of this error if you don't care about it Fixes https://gitlab.com/kicad/code/kicad/-/issues/18058
This commit is contained in:
Seth Hillbrand
parent
e01dfd3158
commit
de8c4d4b01
@ -60,6 +60,7 @@ track_segment_length
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version
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via
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via_count
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via_dangling
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via_diameter
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warning
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within_diff_pairs
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@ -78,7 +78,8 @@ enum DRC_CONSTRAINT_T
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PHYSICAL_HOLE_CLEARANCE_CONSTRAINT,
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ASSERTION_CONSTRAINT,
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CONNECTION_WIDTH_CONSTRAINT,
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TRACK_ANGLE_CONSTRAINT
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TRACK_ANGLE_CONSTRAINT,
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VIA_DANGLING_CONSTRAINT
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};
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@ -496,7 +496,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
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"hole_to_hole, track_width, track_angle, track_segment_length, annular_width, "
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"disallow, zone_connection, thermal_relief_gap, thermal_spoke_width, "
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"min_resolved_spokes, solder_mask_expansion, solder_paste_abs_margin, "
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"solder_paste_rel_margin, length, skew, via_count, via_diameter, "
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"solder_paste_rel_margin, length, skew, via_count, via_dangling, via_diameter, "
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"diff_pair_gap or diff_pair_uncoupled" ) );
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reportError( msg );
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return;
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@ -521,6 +521,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
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case T_connection_width: c.m_Type = CONNECTION_WIDTH_CONSTRAINT; break;
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case T_annular_width: c.m_Type = ANNULAR_WIDTH_CONSTRAINT; break;
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case T_via_diameter: c.m_Type = VIA_DIAMETER_CONSTRAINT; break;
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case T_via_dangling: c.m_Type = VIA_DANGLING_CONSTRAINT; break;
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case T_zone_connection: c.m_Type = ZONE_CONNECTION_CONSTRAINT; break;
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case T_thermal_relief_gap: c.m_Type = THERMAL_RELIEF_GAP_CONSTRAINT; break;
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case T_thermal_spoke_width: c.m_Type = THERMAL_SPOKE_WIDTH_CONSTRAINT; break;
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@ -543,7 +544,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
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"hole_to_hole, track_width, track_angle, track_segment_length, annular_width, "
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"disallow, zone_connection, thermal_relief_gap, thermal_spoke_width, "
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"min_resolved_spokes, solder_mask_expansion, solder_paste_abs_margin, "
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"solder_paste_rel_margin, length, skew, via_count, via_diameter, "
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"solder_paste_rel_margin, length, skew, via_count, via_dangling, via_diameter, "
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"diff_pair_gap or diff_pair_uncoupled" ) );
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reportError( msg );
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}
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@ -556,7 +557,8 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
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bool unitless = c.m_Type == VIA_COUNT_CONSTRAINT
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|| c.m_Type == MIN_RESOLVED_SPOKES_CONSTRAINT
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|| c.m_Type == TRACK_ANGLE_CONSTRAINT;
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|| c.m_Type == TRACK_ANGLE_CONSTRAINT
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|| c.m_Type == VIA_DANGLING_CONSTRAINT;
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allowsTimeDomain = c.m_Type == LENGTH_CONSTRAINT || c.m_Type == SKEW_CONSTRAINT;
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@ -89,7 +89,24 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
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if( connectivity->TestTrackEndpointDangling( track, true, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( code );
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std::shared_ptr<DRC_ITEM> drcItem;
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if( track->Type() == PCB_VIA_T )
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{
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auto constraint = m_drcEngine->EvalRules( VIA_DANGLING_CONSTRAINT, track, nullptr,
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track->GetLayer() );
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
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continue;
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drcItem = DRC_ITEM::Create( code );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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}
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else
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{
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drcItem = DRC_ITEM::Create( code );
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}
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drcItem->SetItems( track );
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reportViolation( drcItem, pos, track->GetLayer() );
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}
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5
qa/data/pcbnew/via_dangling.kicad_dru
Normal file
5
qa/data/pcbnew/via_dangling.kicad_dru
Normal file
@ -0,0 +1,5 @@
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(version 1)
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(rule ignore_left
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(constraint via_dangling)
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(condition "A.Position_X < 20mm")
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(severity ignore))
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137
qa/data/pcbnew/via_dangling.kicad_pcb
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137
qa/data/pcbnew/via_dangling.kicad_pcb
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@ -0,0 +1,137 @@
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(kicad_pcb
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(version 20250901)
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(generator "pcbnew")
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(generator_version "9.99")
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(general
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(thickness 1.6)
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(legacy_teardrops no)
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)
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(paper "A4")
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(layers
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(0 "F.Cu" signal)
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(2 "B.Cu" signal)
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(25 "Edge.Cuts" user)
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(27 "Margin" user)
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(31 "F.CrtYd" user "F.Courtyard")
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(29 "B.CrtYd" user "B.Courtyard")
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)
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(setup
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(pad_to_mask_clearance 0)
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(allow_soldermask_bridges_in_footprints no)
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(tenting
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(front yes)
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(back yes)
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)
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(covering
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(front no)
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(back no)
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)
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(plugging
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(front no)
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(back no)
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)
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(capping no)
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(filling no)
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(pcbplotparams
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(layerselection 0x00000000_00000000_55555555_5755f5ff)
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(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
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(disableapertmacros no)
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(usegerberextensions no)
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(usegerberattributes yes)
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(usegerberadvancedattributes yes)
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(creategerberjobfile yes)
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(dashed_line_dash_ratio 12)
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(dashed_line_gap_ratio 3)
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(svgprecision 4)
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(plotframeref no)
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(mode 1)
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(useauxorigin no)
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(pdf_front_fp_property_popups yes)
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(pdf_back_fp_property_popups yes)
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(pdf_metadata yes)
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(pdf_single_document no)
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(dxfpolygonmode yes)
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(dxfimperialunits yes)
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(dxfusepcbnewfont yes)
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(psnegative no)
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(psa4output no)
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(plot_black_and_white yes)
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(sketchpadsonfab no)
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(plotpadnumbers no)
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(hidednponfab no)
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(sketchdnponfab yes)
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(crossoutdnponfab yes)
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(subtractmaskfromsilk no)
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(outputformat 1)
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(mirror no)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(gr_rect
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(start 0 0)
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(end 40 20)
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(stroke
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(width 0.1)
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(type solid)
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)
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(fill no)
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(layer "Edge.Cuts")
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(uuid "6286fcef-0d96-4ddb-ae43-be4b4ffe718e")
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)
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(segment
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(start 10 10)
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(end 30 10)
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(width 0.2)
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(layer "F.Cu")
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(net 0)
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(uuid "d4a4f87d-990f-4a53-9b82-9a6fc90a1179")
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)
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(via
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(at 30 10)
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(size 0.8)
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(drill 0.4)
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(layers "F.Cu" "B.Cu")
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(tenting
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(front none)
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(back none)
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)
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(capping none)
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(covering
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(front none)
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(back none)
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)
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(plugging
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(front none)
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(back none)
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)
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(filling none)
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(net 0)
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(uuid "0d899acd-71ef-4c82-9710-1acddf041557")
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)
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(via
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(at 10 10)
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(size 0.8)
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(drill 0.4)
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(layers "F.Cu" "B.Cu")
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(tenting
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(front none)
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(back none)
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)
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(capping none)
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(covering
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(front none)
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(back none)
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)
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(plugging
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(front none)
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(back none)
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)
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(filling none)
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(net 0)
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(uuid "d750ed33-4724-448f-b5ca-17da4065fd7e")
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)
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(embedded_fonts no)
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)
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296
qa/data/pcbnew/via_dangling.kicad_pro
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296
qa/data/pcbnew/via_dangling.kicad_pro
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@ -0,0 +1,296 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"apply_defaults_to_fp_fields": false,
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"apply_defaults_to_fp_shapes": false,
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"apply_defaults_to_fp_text": false,
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"board_outline_line_width": 0.05,
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"copper_line_width": 0.2,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.05,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": true,
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"text_position": 0,
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"units_format": 0
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},
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"fab_line_width": 0.1,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.1,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.8,
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"height": 1.27,
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"width": 2.54
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},
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"silk_line_width": 0.1,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.1,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.5
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"creepage": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_filters_mismatch": "ignore",
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"footprint_symbol_mismatch": "warning",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_to_hole": "warning",
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"holes_co_located": "warning",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"mirrored_text_on_front_layer": "warning",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_on_edge_cuts": "error",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_angle": "error",
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"track_dangling": "warning",
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"track_segment_length": "error",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zones_intersect": "error"
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},
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"rules": {
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"max_error": 0.005,
|
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"min_clearance": 0.0,
|
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"min_connection": 0.0,
|
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"min_copper_edge_clearance": 0.5,
|
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"min_groove_width": 0.0,
|
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"min_hole_clearance": 0.25,
|
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"min_hole_to_hole": 0.25,
|
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"min_microvia_diameter": 0.2,
|
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"min_microvia_drill": 0.1,
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"min_resolved_spokes": 2,
|
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"min_silk_clearance": 0.0,
|
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"min_text_height": 0.8,
|
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"min_text_thickness": 0.08,
|
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"min_through_hole_diameter": 0.3,
|
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"min_track_width": 0.0,
|
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"min_via_annular_width": 0.1,
|
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"min_via_diameter": 0.5,
|
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"solder_mask_to_copper_clearance": 0.0,
|
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"use_height_for_length_calcs": true
|
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},
|
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"teardrop_options": [
|
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{
|
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"td_onpthpad": true,
|
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"td_onroundshapesonly": false,
|
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"td_onsmdpad": true,
|
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"td_ontrackend": false,
|
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"td_onvia": true
|
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}
|
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],
|
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"teardrop_parameters": [
|
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{
|
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"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
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"td_maxlen": 1.0,
|
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"td_on_pad_in_zone": false,
|
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"td_target_name": "td_rect_shape",
|
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"td_width_to_size_filter_ratio": 0.9
|
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},
|
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{
|
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"td_allow_use_two_tracks": true,
|
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"td_curve_segcount": 0,
|
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"td_height_ratio": 1.0,
|
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"td_length_ratio": 0.5,
|
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"td_maxheight": 2.0,
|
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"td_maxlen": 1.0,
|
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"td_on_pad_in_zone": false,
|
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"td_target_name": "td_track_end",
|
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"td_width_to_size_filter_ratio": 0.9
|
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}
|
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],
|
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"track_widths": [],
|
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"tuning_pattern_settings": {
|
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"diff_pair_defaults": {
|
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"corner_radius_percentage": 80,
|
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"corner_style": 1,
|
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"max_amplitude": 1.0,
|
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"min_amplitude": 0.2,
|
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"single_sided": false,
|
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"spacing": 1.0
|
||||
},
|
||||
"diff_pair_skew_defaults": {
|
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"corner_radius_percentage": 80,
|
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"corner_style": 1,
|
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"max_amplitude": 1.0,
|
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"min_amplitude": 0.2,
|
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"single_sided": false,
|
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"spacing": 0.6
|
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},
|
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"single_track_defaults": {
|
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"corner_radius_percentage": 80,
|
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"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
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"min_amplitude": 0.2,
|
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"single_sided": false,
|
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"spacing": 0.6
|
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}
|
||||
},
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"component_class_settings": {
|
||||
"assignments": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"sheet_component_classes": {
|
||||
"enabled": false
|
||||
}
|
||||
},
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "via_dangling.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 5
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"specctra_dsn": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {},
|
||||
"time_domain_parameters": {
|
||||
"delay_profiles_user_defined": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -73,6 +73,7 @@ set( QA_PCBNEW_SRCS
|
||||
drc/test_drc_orientation.cpp
|
||||
drc/test_drc_lengths.cpp
|
||||
drc/test_drc_unconnected_items_exclusion_loss.cpp
|
||||
drc/test_drc_via_dangling.cpp
|
||||
|
||||
pcb_io/altium/test_altium_rule_transformer.cpp
|
||||
pcb_io/altium/test_altium_pcblib_import.cpp
|
||||
|
||||
86
qa/tests/pcbnew/drc/test_drc_via_dangling.cpp
Normal file
86
qa/tests/pcbnew/drc/test_drc_via_dangling.cpp
Normal file
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||
*
|
||||
* Copyright The KiCad Developers.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, you may find one here:
|
||||
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
|
||||
* or you may search the http://www.gnu.org website for the version 2 license,
|
||||
* or you may write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||
#include <pcbnew_utils/board_test_utils.h>
|
||||
#include <board.h>
|
||||
#include <board_design_settings.h>
|
||||
#include <pcb_marker.h>
|
||||
#include <drc/drc_item.h>
|
||||
#include <settings/settings_manager.h>
|
||||
|
||||
struct DRC_REGRESSION_TEST_FIXTURE
|
||||
{
|
||||
DRC_REGRESSION_TEST_FIXTURE() :
|
||||
m_settingsManager( true /* headless */ )
|
||||
{ }
|
||||
|
||||
SETTINGS_MANAGER m_settingsManager;
|
||||
std::unique_ptr<BOARD> m_board;
|
||||
};
|
||||
|
||||
BOOST_FIXTURE_TEST_CASE( DRCViaDanglingRuleTest, DRC_REGRESSION_TEST_FIXTURE )
|
||||
{
|
||||
KI_TEST::LoadBoard( m_settingsManager, "via_dangling", m_board );
|
||||
|
||||
std::vector<DRC_ITEM> violations;
|
||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||
|
||||
bds.m_DRCEngine->SetViolationHandler(
|
||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, VECTOR2I aPos, int aLayer,
|
||||
DRC_CUSTOM_MARKER_HANDLER* aCustomHandler )
|
||||
{
|
||||
PCB_MARKER temp( aItem, aPos );
|
||||
|
||||
if( bds.m_DrcExclusions.find( temp.SerializeToString() ) == bds.m_DrcExclusions.end() )
|
||||
violations.push_back( *aItem );
|
||||
} );
|
||||
|
||||
bds.m_DRCEngine->RunTests( EDA_UNITS::MM, true, false );
|
||||
|
||||
int danglingVias = 0;
|
||||
|
||||
for( const DRC_ITEM& item : violations )
|
||||
{
|
||||
if( item.GetErrorCode() == DRCE_DANGLING_VIA )
|
||||
danglingVias++;
|
||||
}
|
||||
|
||||
if( danglingVias == 1 && violations.size() == 1 )
|
||||
{
|
||||
BOOST_CHECK_EQUAL( 1, 1 );
|
||||
BOOST_TEST_MESSAGE( "Via dangling rule test passed" );
|
||||
}
|
||||
else
|
||||
{
|
||||
UNITS_PROVIDER unitsProvider( pcbIUScale, EDA_UNITS::INCH );
|
||||
|
||||
std::map<KIID, EDA_ITEM*> itemMap;
|
||||
m_board->FillItemMap( itemMap );
|
||||
|
||||
for( const DRC_ITEM& item : violations )
|
||||
BOOST_TEST_MESSAGE( item.ShowReport( &unitsProvider, RPT_SEVERITY_ERROR, itemMap ) );
|
||||
|
||||
BOOST_ERROR( "Via dangling rule test failed" );
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user