Merge branch 'master' into 'master'

Refactor pad thickness calculations to use actual copper thickness instead of...

See merge request kicad/code/kicad!2262

common/jobs/job_export_pcb_3d.h

@@ -56,6 +56,7 @@ public:
             m_FuseShapes( false ),
             m_FillAllVias( false ),
             m_OptimizeStep( true ),
+            m_ExtraPadThickness( true ),
             m_Format( FORMAT::STEP ),
             m_OutputFile()
     {};
@@ -98,6 +99,7 @@ public:
     bool     m_FuseShapes;
     bool     m_FillAllVias;
     bool     m_OptimizeStep;
+    bool     m_ExtraPadThickness;
     FORMAT   m_Format;
     wxString m_OutputFile;
 

kicad/cli/command_pcb_export_3d.cpp

@@ -50,6 +50,7 @@
 #define ARG_FUSE_SHAPES "--fuse-shapes"
 #define ARG_FILL_ALL_VIAS "--fill-all-vias"
 #define ARG_NO_OPTIMIZE_STEP "--no-optimize-step"
+#define ARG_NO_EXTRA_PAD_THICKNESS "--no-extra-pad-thickness"
 #define ARG_NET_FILTER "--net-filter"
 #define ARG_FORMAT "--format"
 #define ARG_VRML_UNITS "--units"
@@ -165,6 +166,10 @@ CLI::PCB_EXPORT_3D_COMMAND::PCB_EXPORT_3D_COMMAND( const std::string&        aNa
                 .help( UTF8STDSTR( _( "Don't cut via holes in conductor layers." ) ) )
                 .flag();
 
+        m_argParser.add_argument( ARG_NO_EXTRA_PAD_THICKNESS )
+                .help( UTF8STDSTR( _( "Disable extra pad thickness (pads will have normal thickness)" ) ) )
+                .flag();
+
         m_argParser.add_argument( ARG_MIN_DISTANCE )
                 .default_value( std::string( "0.01mm" ) )
                 .help( UTF8STDSTR( _( "Minimum distance between points to treat them as separate "
@@ -231,6 +236,7 @@ int CLI::PCB_EXPORT_3D_COMMAND::doPerform( KIWAY& aKiway )
         params.m_ExportSoldermask = m_argParser.get<bool>( ARG_INCLUDE_SOLDERMASK );
         params.m_FuseShapes = m_argParser.get<bool>( ARG_FUSE_SHAPES );
         params.m_FillAllVias = m_argParser.get<bool>( ARG_FILL_ALL_VIAS );
+        params.m_ExtraPadThickness = !m_argParser.get<bool>( ARG_NO_EXTRA_PAD_THICKNESS );
         params.m_BoardOnly = m_argParser.get<bool>( ARG_BOARD_ONLY );
         params.m_NetFilter = From_UTF8( m_argParser.get<std::string>( ARG_NET_FILTER ).c_str() );
         params.m_ComponentFilter =

pcbnew/exporters/step/exporter_step.cpp

@@ -725,6 +725,7 @@ bool EXPORTER_STEP::buildBoard3DShapes()
     m_pcbModel->SetEnabledLayers( m_layersToExport );
     m_pcbModel->SetFuseShapes( m_params.m_FuseShapes );
     m_pcbModel->SetNetFilter( m_params.m_NetFilter );
+    m_pcbModel->SetExtraPadThickness( m_params.m_ExtraPadThickness );
 
     // Note: m_params.m_BoardOutlinesChainingEpsilon is used only to build the board outlines,
     // not to set OCC chaining epsilon (much smaller)

pcbnew/exporters/step/step_pcb_model.cpp

@@ -786,6 +786,7 @@ STEP_PCB_MODEL::STEP_PCB_MODEL( const wxString& aPcbName, REPORTER* aReporter )
     m_minx = 1.0e10;    // absurdly large number; any valid PCB X value will be smaller
     m_pcbName = aPcbName;
     m_fuseShapes = false;
+    m_extraPadThickness = true;
     m_outFmt = OUTPUT_FORMAT::FMT_OUT_UNKNOWN;
 }
 
@@ -819,7 +820,7 @@ bool STEP_PCB_MODEL::AddPadShape( const PAD* aPad, const VECTOR2D& aOrigin, bool
         double Zpos, thickness;
         getLayerZPlacement( pcb_layer, Zpos, thickness );
 
-        if( !aVia )
+        if( !aVia && m_extraPadThickness )
         {
             // Pad surface as a separate face for FEM simulations.
             if( pcb_layer == F_Cu )
@@ -883,7 +884,7 @@ bool STEP_PCB_MODEL::AddPadShape( const PAD* aPad, const VECTOR2D& aOrigin, bool
         getLayerZPlacement( F_Cu, f_pos, f_thickness );
         getLayerZPlacement( B_Cu, b_pos, b_thickness );
 
-        if( !aVia )
+        if( !aVia && m_extraPadThickness )
         {
             // Pad surface is slightly thicker
             f_thickness += c_padExtraThickness;
@@ -979,7 +980,7 @@ bool STEP_PCB_MODEL::AddHole( const SHAPE_SEGMENT& aShape, int aPlatingThickness
                            // must be > OCC_MAX_DISTANCE_TO_MERGE_POINTS
 
     // Pads are taller by 0.01 mm
-    if( !aVia )
+    if( !aVia && m_extraPadThickness)
         margin += 0.01;
 
     double f_pos, f_thickness;
@@ -1295,6 +1296,12 @@ void STEP_PCB_MODEL::SetNetFilter( const wxString& aFilter )
 }
 
 
+void STEP_PCB_MODEL::SetExtraPadThickness( bool aValue )
+{
+    m_extraPadThickness = aValue;
+}
+
+
 void STEP_PCB_MODEL::SetCopperColor( double r, double g, double b )
 {
     m_copperColor[0] = r;

pcbnew/exporters/step/step_pcb_model.h

@@ -128,6 +128,7 @@ public:
     void SetSimplifyShapes( bool aValue );
     void SetStackup( const BOARD_STACKUP& aStackup );
     void SetNetFilter( const wxString& aFilter );
+    void SetExtraPadThickness( bool aValue );
 
     // Set the max distance (in mm) to consider 2 points have the same coordinates
     // and can be merged
@@ -260,6 +261,7 @@ private:
     bool                            m_hasPCB;           // set true if CreatePCB() has been invoked
     bool                            m_simplifyShapes;   // convert parts of outlines to arcs where possible
     bool                            m_fuseShapes;       // fuse geometry together
+    bool                            m_extraPadThickness; // add extra thickness to pads equal to copper thickness
     std::vector<TDF_Label>          m_pcb_labels;       // labels for the PCB model (one by main outline)
     MODEL_MAP                       m_models;           // map of file names to model labels
     int                             m_components;       // number of successfully loaded components;