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https://gitlab.com/kicad/code/kicad.git
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7311f07eaf
*) Extend SWIG support deeper into the BOARD class.
*) Move swig *.i files into a directory identified for SWIG, in preparation
for a parallel universe involving Phoenix's SIP.
*) Move swig files which will be common to both eeschema and pcbnew into
common/swig.
*) Sketch out a "common" python module, and plan on dovetailing that into a
libkicad_shared.{dll,so}
*) Add common/swig/ki_exceptions.i and define a macro HANDLE_EXCEPTIONS()
which is to be applied to any function which needs C++ to python
exception translation.
*) Move the test for SWIG tool into top level CMakeLists.txt file for use
in all python modules beyond pcbnew, i.e. eeschema and common.
*) Add SWIG_MODULE_pcbnew_EXTRA_DEPS which generates a better Makefile, one
which rebuilds the swig generated *.cxx file when one of its dependencies
change.
*) Re-architect the board.i file so that it can be split into multiple *.i
files easily.
*) Make some KIWAY from python progress, in preparation for Modular KiCad
phase III.
67 lines
1.6 KiB
Python
67 lines
1.6 KiB
Python
#!/usr/bin/env python
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import sys
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from pcbnew import *
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filename=sys.argv[1]
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pcb = LoadBoard(filename)
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ToUnits = ToMM
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FromUnits = FromMM
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#ToUnits=ToMils
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#FromUnits=FromMils
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print "LISTING VIAS:"
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for item in pcb.GetTracks():
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if type(item) is VIA:
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pos = item.GetPosition()
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drill = item.GetDrillValue()
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width = item.GetWidth()
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print " * Via: %s - %f/%f "%(ToUnits(pos),ToUnits(drill),ToUnits(width))
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elif type(item) is TRACK:
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start = item.GetStart()
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end = item.GetEnd()
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width = item.GetWidth()
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print " * Track: %s to %s, width %f" % (ToUnits(start),ToUnits(end),ToUnits(width))
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else:
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print "Unknown type %s" % type(item)
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print ""
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print "LIST DRAWINGS:"
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for item in pcb.GetDrawings():
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if type(item) is TEXTE_PCB:
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print "* Text: '%s' at %s"%(item.GetText(), item.GetPosition())
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elif type(item) is DRAWSEGMENT:
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print "* Drawing: %s"%item.GetShapeStr() # dir(item)
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else:
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print type(item)
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print ""
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print "LIST MODULES:"
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for module in pcb.GetModules():
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print "* Module: %s at %s"%(module.GetReference(),ToUnits(module.GetPosition()))
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print ""
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print "Ratsnest cnt:",len(pcb.GetFullRatsnest())
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print "track w cnt:",len(pcb.GetTrackWidthList())
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print "via s cnt:",len(pcb.GetViasDimensionsList())
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print ""
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print "LIST ZONES:", pcb.GetAreaCount()
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for idx in range(0, pcb.GetAreaCount()):
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zone=pcb.GetArea(idx)
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print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname()
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print ""
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print "NetClasses:", pcb.GetNetClasses().GetCount(),
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