mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-13 17:53:11 +02:00
f66cbaf43a
Implement bracket notation for stacked pins ([1,2,3], [1-4], [1,3,5-7]). Automatic net naming proceeds based on the smallest logical pin number in stacked groups. Provide explode/reform commands in symbol editor for conversion. Supports arbitrary ranges including BGA alphanum ranges like [AA1-AA3,CD14-CD22] Adds some additional QA and trace logging Fixes https://gitlab.com/kicad/code/kicad/-/issues/2004
345 lines
9.0 KiB
C++
345 lines
9.0 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 1992-2011 Jean-Pierre Charras.
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* Copyright (C) 2013 Wayne Stambaugh <stambaughw@gmail.com>.
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* Copyright The KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "pcb_netlist.h"
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#include <footprint.h>
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#include <richio.h>
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#include <string_utils.h>
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#include <wx/tokenzr.h>
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#include <wx/log.h>
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int COMPONENT_NET::Format( OUTPUTFORMATTER* aOut, int aNestLevel, int aCtl )
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{
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return aOut->Print( aNestLevel, "(pin_net %s %s)",
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aOut->Quotew( m_pinName ).c_str(),
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aOut->Quotew( m_netName ).c_str() );
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}
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void COMPONENT::SetFootprint( FOOTPRINT* aFootprint )
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{
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m_footprint.reset( aFootprint );
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KIID_PATH path = m_path;
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if( !m_kiids.empty() )
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path.push_back( m_kiids.front() );
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if( aFootprint == nullptr )
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return;
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aFootprint->SetReference( m_reference );
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aFootprint->SetValue( m_value );
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aFootprint->SetFPID( m_fpid );
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aFootprint->SetPath( path );
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}
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COMPONENT_NET COMPONENT::m_emptyNet;
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const COMPONENT_NET& COMPONENT::GetNet( const wxString& aPinName ) const
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( "Looking for pin '%s' in component '%s'" ),
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aPinName, m_reference );
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for( const COMPONENT_NET& net : m_nets )
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " Checking net pin name '%s'" ),
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net.GetPinName() );
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if( net.GetPinName() == aPinName )
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " Found exact match for pin '%s'" ),
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aPinName );
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return net;
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}
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// Check if this net's pin name is a stacked pin notation that expands to include aPinName
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std::vector<wxString> expandedPins = ExpandStackedPinNotation( net.GetPinName() );
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if( !expandedPins.empty() )
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " Pin name '%s' expanded to %zu pins" ),
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net.GetPinName(), expandedPins.size() );
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for( const wxString& expandedPin : expandedPins )
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " Checking expanded pin '%s'" ),
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expandedPin );
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if( expandedPin == aPinName )
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{
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " Found match for pin '%s' in stacked notation '%s'" ),
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aPinName, net.GetPinName() );
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return net;
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}
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}
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}
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}
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wxLogTrace( wxT( "NETLIST_STACKED_PINS" ),
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wxT( " No net found for pin '%s'" ),
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aPinName );
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return m_emptyNet;
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}
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void COMPONENT::Format( OUTPUTFORMATTER* aOut, int aNestLevel, int aCtl )
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{
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int nl = aNestLevel;
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aOut->Print( nl, "(ref %s ", aOut->Quotew( m_reference ).c_str() );
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aOut->Print( 0, "(fpid %s)\n", aOut->Quotew( m_fpid.Format() ).c_str() );
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if( !( aCtl & CTL_OMIT_EXTRA ) )
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{
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aOut->Print( nl+1, "(value %s)\n", aOut->Quotew( m_value ).c_str() );
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aOut->Print( nl+1, "(name %s)\n", aOut->Quotew( m_name ).c_str() );
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aOut->Print( nl+1, "(library %s)\n", aOut->Quotew( m_library ).c_str() );
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wxString path;
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for( const KIID& pathStep : m_path )
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path += '/' + pathStep.AsString();
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if( !( aCtl & CTL_OMIT_FP_UUID ) && !m_kiids.empty() )
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path += '/' + m_kiids.front().AsString();
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aOut->Print( nl+1, "(timestamp %s)\n", aOut->Quotew( path ).c_str() );
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// Add all fields as a (field) under a (fields) node
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aOut->Print( nl + 1, "(fields" );
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for( std::pair<wxString, wxString> field : m_fields )
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aOut->Print( nl + 2, "\n(field (name %s) %s)", aOut->Quotew( field.first ).c_str(),
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aOut->Quotew( field.second ).c_str() );
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aOut->Print( 0, ")\n" );
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// Add DNP and Exclude from BOM properties if we have them
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if( m_properties.count( "dnp" ) )
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aOut->Print( nl + 1, "(property (name \"dnp\"))\n" );
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if( m_properties.count( "exclude_from_bom" ) )
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aOut->Print( nl + 1, "(property (name \"exclude_from_bom\"))\n" );
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}
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if( !( aCtl & CTL_OMIT_FILTERS ) && m_footprintFilters.GetCount() )
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{
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aOut->Print( nl+1, "(fp_filters" );
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for( unsigned i = 0; i < m_footprintFilters.GetCount(); ++i )
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aOut->Print( 0, " %s", aOut->Quotew( m_footprintFilters[i] ).c_str() );
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aOut->Print( 0, ")\n" );
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}
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if( !( aCtl & CTL_OMIT_NETS ) && m_nets.size() )
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{
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int llen = aOut->Print( nl+1, "(nets " );
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for( unsigned i = 0; i < m_nets.size(); ++i )
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{
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if( llen > 80 )
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{
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aOut->Print( 0, "\n" );
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llen = aOut->Print( nl+1, " " );
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}
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llen += m_nets[i].Format( aOut, 0, aCtl );
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}
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aOut->Print( 0, ")\n" );
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}
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aOut->Print( nl, ")\n" ); // </ref>
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}
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void NETLIST::Format( const char* aDocName, OUTPUTFORMATTER* aOut, int aNestLevel, int aCtl )
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{
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int nl = aNestLevel;
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aOut->Print( nl, "(%s\n", aDocName );
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for( unsigned i = 0; i < m_components.size(); i++ )
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{
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m_components[i].Format( aOut, nl+1, aCtl );
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}
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aOut->Print( nl, ")\n" );
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}
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void NETLIST::AddComponent( COMPONENT* aComponent )
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{
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m_components.push_back( aComponent );
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}
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void NETLIST::AddGroup( NETLIST_GROUP* aComponent )
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{
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m_groups.push_back( aComponent );
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}
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NETLIST_GROUP* NETLIST::GetGroupByUuid( const KIID& aUuid )
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{
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for( NETLIST_GROUP& group : m_groups )
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{
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if( group.uuid == aUuid )
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return &group;
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}
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return nullptr;
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}
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COMPONENT* NETLIST::GetComponentByReference( const wxString& aReference )
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{
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COMPONENT* component = nullptr;
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for( unsigned i = 0; i < m_components.size(); i++ )
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{
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if( m_components[i].GetReference() == aReference )
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{
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component = &m_components[i];
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break;
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}
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}
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return component;
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}
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COMPONENT* NETLIST::GetComponentByPath( const KIID_PATH& aUuidPath )
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{
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if( aUuidPath.empty() )
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return nullptr;
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KIID comp_uuid = aUuidPath.back();
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KIID_PATH base = aUuidPath;
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if( !base.empty() )
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base.pop_back();
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for( COMPONENT& component : m_components )
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{
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const std::vector<KIID>& kiids = component.GetKIIDs();
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if( base != component.GetPath() )
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continue;
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if( std::find( kiids.begin(), kiids.end(), comp_uuid ) != kiids.end() )
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return &component;
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}
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return nullptr;
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}
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COMPONENT* NETLIST::GetComponentByUuid( const KIID& aUuid)
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{
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if( aUuid == 0 )
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return nullptr;
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for( COMPONENT& component : m_components )
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{
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for( const KIID& compUuid : component.GetKIIDs() )
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{
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if( aUuid == compUuid )
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return &component;
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}
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}
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return nullptr;
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}
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/**
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* A helper function used to sort the component list used by loadNewModules.
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*/
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static bool ByFPID( const COMPONENT& ref, const COMPONENT& cmp )
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{
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return ref.GetFPID() > cmp.GetFPID();
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}
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void NETLIST::SortByFPID()
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{
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m_components.sort( ByFPID );
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}
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/**
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* Compare two #COMPONENT objects by reference designator.
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*/
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bool operator < ( const COMPONENT& item1, const COMPONENT& item2 )
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{
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return StrNumCmp( item1.GetReference(), item2.GetReference(), true ) < 0;
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}
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void NETLIST::SortByReference()
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{
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m_components.sort();
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}
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bool NETLIST::AnyFootprintsLinked() const
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{
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for( unsigned i = 0; i < m_components.size(); i++ )
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{
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if( !m_components[i].GetFPID().empty() )
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return true;
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}
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return false;
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}
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void NETLIST::ApplyGroupMembership()
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{
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for( NETLIST_GROUP& group : m_groups )
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{
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for( KIID& member : group.members )
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{
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COMPONENT* component = GetComponentByUuid( member );
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if( component )
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component->SetGroup( &group );
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}
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}
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}
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