mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-14 10:13:19 +02:00
ede39780e2
The use of printf, wxLogDebug, and std::err/std::out causes excessive debugging output which makes finding specific debugging messages more difficult than it needs to be. There is still some debugging output in test code that really needs to be moved into a unit test. Add debugging output section to the coding policy regarding debugging output.
783 lines
21 KiB
C++
783 lines
21 KiB
C++
/*
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* This program source code file is part of KICAD, a free EDA CAD application.
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*
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* Copyright (C) 2016-2018 CERN
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* Copyright (C) 2020 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* @author Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <connectivity/connectivity_algo.h>
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#include <widgets/progress_reporter.h>
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#include <geometry/geometry_utils.h>
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#include <board_commit.h>
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#include <thread>
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#include <mutex>
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#include <algorithm>
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#include <future>
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#ifdef PROFILE
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#include <profile.h>
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#endif
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bool CN_CONNECTIVITY_ALGO::Remove( BOARD_ITEM* aItem )
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{
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markItemNetAsDirty( aItem );
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switch( aItem->Type() )
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{
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case PCB_MODULE_T:
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for( auto pad : static_cast<MODULE*>( aItem ) -> Pads() )
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{
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m_itemMap[pad].MarkItemsAsInvalid();
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m_itemMap.erase( pad );
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}
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m_itemList.SetDirty( true );
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break;
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case PCB_PAD_T:
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m_itemMap[aItem].MarkItemsAsInvalid();
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m_itemMap.erase( aItem );
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m_itemList.SetDirty( true );
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break;
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case PCB_TRACE_T:
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case PCB_ARC_T:
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m_itemMap[aItem].MarkItemsAsInvalid();
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m_itemMap.erase( aItem );
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m_itemList.SetDirty( true );
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break;
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case PCB_VIA_T:
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m_itemMap[aItem].MarkItemsAsInvalid();
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m_itemMap.erase( aItem );
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m_itemList.SetDirty( true );
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break;
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case PCB_ZONE_AREA_T:
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{
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m_itemMap[aItem].MarkItemsAsInvalid();
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m_itemMap.erase ( aItem );
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m_itemList.SetDirty( true );
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break;
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}
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default:
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return false;
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}
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// Once we delete an item, it may connect between lists, so mark both as potentially invalid
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m_itemList.SetHasInvalid( true );
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return true;
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}
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void CN_CONNECTIVITY_ALGO::markItemNetAsDirty( const BOARD_ITEM* aItem )
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{
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if( aItem->IsConnected() )
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{
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auto citem = static_cast<const BOARD_CONNECTED_ITEM*>( aItem );
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MarkNetAsDirty( citem->GetNetCode() );
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}
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else
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{
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if( aItem->Type() == PCB_MODULE_T )
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{
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auto mod = static_cast <const MODULE*>( aItem );
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for( auto pad : mod->Pads() )
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MarkNetAsDirty( pad->GetNetCode() );
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}
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}
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}
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bool CN_CONNECTIVITY_ALGO::Add( BOARD_ITEM* aItem )
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{
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if( !aItem->IsOnCopperLayer() )
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return false;
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markItemNetAsDirty ( aItem );
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switch( aItem->Type() )
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{
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case PCB_NETINFO_T:
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{
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MarkNetAsDirty( static_cast<NETINFO_ITEM*>( aItem )->GetNet() );
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break;
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}
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case PCB_MODULE_T:
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for( auto pad : static_cast<MODULE*>( aItem ) -> Pads() )
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{
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if( m_itemMap.find( pad ) != m_itemMap.end() )
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return false;
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add( m_itemList, pad );
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}
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break;
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case PCB_PAD_T:
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if( m_itemMap.find ( aItem ) != m_itemMap.end() )
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return false;
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add( m_itemList, static_cast<D_PAD*>( aItem ) );
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break;
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case PCB_TRACE_T:
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{
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if( m_itemMap.find( aItem ) != m_itemMap.end() )
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return false;
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add( m_itemList, static_cast<TRACK*>( aItem ) );
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break;
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}
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case PCB_ARC_T:
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{
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if( m_itemMap.find( aItem ) != m_itemMap.end() )
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return false;
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add( m_itemList, static_cast<ARC*>( aItem ) );
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break;
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}
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case PCB_VIA_T:
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if( m_itemMap.find( aItem ) != m_itemMap.end() )
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return false;
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add( m_itemList, static_cast<VIA*>( aItem ) );
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break;
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case PCB_ZONE_AREA_T:
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{
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auto zone = static_cast<ZONE_CONTAINER*>( aItem );
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if( m_itemMap.find( aItem ) != m_itemMap.end() )
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return false;
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m_itemMap[zone] = ITEM_MAP_ENTRY();
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for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
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for( auto zitem : m_itemList.Add( zone, layer ) )
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m_itemMap[zone].Link( zitem );
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break;
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}
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default:
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return false;
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}
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return true;
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}
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void CN_CONNECTIVITY_ALGO::searchConnections()
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{
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#ifdef PROFILE
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PROF_COUNTER garbage_collection( "garbage-collection" );
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#endif
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std::vector<CN_ITEM*> garbage;
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garbage.reserve( 1024 );
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m_itemList.RemoveInvalidItems( garbage );
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for( auto item : garbage )
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delete item;
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#ifdef PROFILE
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garbage_collection.Show();
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PROF_COUNTER search_basic( "search-basic" );
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#endif
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std::vector<CN_ITEM*> dirtyItems;
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std::copy_if( m_itemList.begin(), m_itemList.end(), std::back_inserter( dirtyItems ),
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[] ( CN_ITEM* aItem ) { return aItem->Dirty(); } );
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if( m_progressReporter )
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{
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m_progressReporter->SetMaxProgress( dirtyItems.size() );
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m_progressReporter->KeepRefreshing();
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}
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if( m_itemList.IsDirty() )
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{
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size_t parallelThreadCount = std::min<size_t>( std::thread::hardware_concurrency(),
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( dirtyItems.size() + 7 ) / 8 );
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std::atomic<size_t> nextItem( 0 );
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std::vector<std::future<size_t>> returns( parallelThreadCount );
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auto conn_lambda = [&nextItem, &dirtyItems]
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( CN_LIST* aItemList, PROGRESS_REPORTER* aReporter) -> size_t
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{
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for( size_t i = nextItem++; i < dirtyItems.size(); i = nextItem++ )
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{
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CN_VISITOR visitor( dirtyItems[i] );
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aItemList->FindNearby( dirtyItems[i], visitor );
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if( aReporter )
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aReporter->AdvanceProgress();
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}
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return 1;
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};
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if( parallelThreadCount <= 1 )
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conn_lambda( &m_itemList, m_progressReporter );
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else
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{
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for( size_t ii = 0; ii < parallelThreadCount; ++ii )
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returns[ii] = std::async( std::launch::async, conn_lambda,
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&m_itemList, m_progressReporter );
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for( size_t ii = 0; ii < parallelThreadCount; ++ii )
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{
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// Here we balance returns with a 100ms timeout to allow UI updating
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std::future_status status;
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do
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{
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if( m_progressReporter )
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m_progressReporter->KeepRefreshing();
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status = returns[ii].wait_for( std::chrono::milliseconds( 100 ) );
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} while( status != std::future_status::ready );
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}
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}
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if( m_progressReporter )
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m_progressReporter->KeepRefreshing();
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}
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#ifdef PROFILE
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search_basic.Show();
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#endif
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m_itemList.ClearDirtyFlags();
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}
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const CN_CONNECTIVITY_ALGO::CLUSTERS CN_CONNECTIVITY_ALGO::SearchClusters( CLUSTER_SEARCH_MODE aMode )
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{
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constexpr KICAD_T types[] =
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{ PCB_TRACE_T, PCB_ARC_T, PCB_PAD_T, PCB_VIA_T, PCB_ZONE_AREA_T, PCB_MODULE_T, EOT };
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constexpr KICAD_T no_zones[] =
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{ PCB_TRACE_T, PCB_ARC_T, PCB_PAD_T, PCB_VIA_T, PCB_MODULE_T, EOT };
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if( aMode == CSM_PROPAGATE )
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return SearchClusters( aMode, no_zones, -1 );
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else
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return SearchClusters( aMode, types, -1 );
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}
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const CN_CONNECTIVITY_ALGO::CLUSTERS CN_CONNECTIVITY_ALGO::SearchClusters( CLUSTER_SEARCH_MODE aMode,
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const KICAD_T aTypes[], int aSingleNet )
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{
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bool withinAnyNet = ( aMode != CSM_PROPAGATE );
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std::deque<CN_ITEM*> Q;
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std::set<CN_ITEM*> item_set;
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CLUSTERS clusters;
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if( m_itemList.IsDirty() )
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searchConnections();
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auto addToSearchList = [&item_set, withinAnyNet, aSingleNet, aTypes] ( CN_ITEM *aItem )
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{
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if( withinAnyNet && aItem->Net() <= 0 )
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return;
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if( !aItem->Valid() )
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return;
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if( aSingleNet >=0 && aItem->Net() != aSingleNet )
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return;
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bool found = false;
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for( int i = 0; aTypes[i] != EOT; i++ )
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{
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if( aItem->Parent()->Type() == aTypes[i] )
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{
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found = true;
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break;
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}
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}
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if( !found )
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return;
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aItem->SetVisited( false );
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item_set.insert( aItem );
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};
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std::for_each( m_itemList.begin(), m_itemList.end(), addToSearchList );
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while( !item_set.empty() )
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{
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CN_CLUSTER_PTR cluster ( new CN_CLUSTER() );
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CN_ITEM* root;
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auto it = item_set.begin();
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while( it != item_set.end() && (*it)->Visited() )
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it = item_set.erase( item_set.begin() );
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if( it == item_set.end() )
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break;
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root = *it;
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root->SetVisited ( true );
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Q.clear();
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Q.push_back( root );
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while( Q.size() )
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{
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CN_ITEM* current = Q.front();
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Q.pop_front();
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cluster->Add( current );
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for( auto n : current->ConnectedItems() )
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{
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if( withinAnyNet && n->Net() != root->Net() )
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continue;
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if( !n->Visited() && n->Valid() )
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{
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n->SetVisited( true );
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Q.push_back( n );
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}
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}
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}
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clusters.push_back( cluster );
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}
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std::sort( clusters.begin(), clusters.end(), []( CN_CLUSTER_PTR a, CN_CLUSTER_PTR b ) {
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return a->OriginNet() < b->OriginNet();
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} );
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return clusters;
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}
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void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard )
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{
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for( int i = 0; i<aBoard->GetAreaCount(); i++ )
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{
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auto zone = aBoard->GetArea( i );
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Add( zone );
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}
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for( auto tv : aBoard->Tracks() )
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Add( tv );
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for( auto mod : aBoard->Modules() )
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{
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for( auto pad : mod->Pads() )
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Add( pad );
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}
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/*wxLogTrace( "CN", "zones : %lu, pads : %lu vias : %lu tracks : %lu\n",
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m_zoneList.Size(), m_padList.Size(),
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m_viaList.Size(), m_trackList.Size() );*/
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}
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void CN_CONNECTIVITY_ALGO::Build( const std::vector<BOARD_ITEM*>& aItems )
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{
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for( auto item : aItems )
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{
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switch( item->Type() )
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{
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case PCB_TRACE_T:
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case PCB_ARC_T:
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case PCB_VIA_T:
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case PCB_PAD_T:
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Add( item );
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break;
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case PCB_MODULE_T:
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{
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for( auto pad : static_cast<MODULE*>( item )->Pads() )
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{
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Add( pad );
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}
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break;
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}
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default:
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break;
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}
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}
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}
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void CN_CONNECTIVITY_ALGO::propagateConnections( BOARD_COMMIT* aCommit )
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{
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for( const auto& cluster : m_connClusters )
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{
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if( cluster->IsConflicting() )
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{
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wxLogTrace( "CN", "Conflicting nets in cluster %p\n", cluster.get() );
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}
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else if( cluster->IsOrphaned() )
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{
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wxLogTrace( "CN", "Skipping orphaned cluster %p [net: %s]\n", cluster.get(),
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(const char*) cluster->OriginNetName().c_str() );
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}
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else if( cluster->HasValidNet() )
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{
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// normal cluster: just propagate from the pads
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int n_changed = 0;
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for( auto item : *cluster )
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{
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if( item->CanChangeNet() )
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{
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if( item->Valid() && item->Parent()->GetNetCode() != cluster->OriginNet() )
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{
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MarkNetAsDirty( item->Parent()->GetNetCode() );
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MarkNetAsDirty( cluster->OriginNet() );
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if( aCommit )
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aCommit->Modify( item->Parent() );
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item->Parent()->SetNetCode( cluster->OriginNet() );
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n_changed++;
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}
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}
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}
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if( n_changed )
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{
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wxLogTrace( "CN", "Cluster %p : net : %d %s\n", cluster.get(),
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cluster->OriginNet(), (const char*) cluster->OriginNetName().c_str() );
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}
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else
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wxLogTrace( "CN", "Cluster %p : nothing to propagate\n", cluster.get() );
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}
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else
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{
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wxLogTrace( "CN", "Cluster %p : connected to unused net\n", cluster.get() );
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}
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}
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}
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void CN_CONNECTIVITY_ALGO::PropagateNets( BOARD_COMMIT* aCommit )
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{
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m_connClusters = SearchClusters( CSM_PROPAGATE );
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propagateConnections( aCommit );
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}
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void CN_CONNECTIVITY_ALGO::FindIsolatedCopperIslands( ZONE_CONTAINER* aZone,
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PCB_LAYER_ID aLayer,
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std::vector<int>& aIslands )
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{
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if( aZone->GetFilledPolysList( aLayer ).IsEmpty() )
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return;
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aIslands.clear();
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Remove( aZone );
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Add( aZone );
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m_connClusters = SearchClusters( CSM_CONNECTIVITY_CHECK );
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for( const auto& cluster : m_connClusters )
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{
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if( cluster->Contains( aZone ) && cluster->IsOrphaned() )
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{
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for( auto z : *cluster )
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{
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if( z->Parent() == aZone && z->Layer() == aLayer )
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{
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aIslands.push_back( static_cast<CN_ZONE*>(z)->SubpolyIndex() );
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}
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}
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}
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}
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wxLogTrace( "CN", "Found %u isolated islands\n", (unsigned)aIslands.size() );
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}
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void CN_CONNECTIVITY_ALGO::FindIsolatedCopperIslands( std::vector<CN_ZONE_ISOLATED_ISLAND_LIST>& aZones )
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{
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for( auto& z : aZones )
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{
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Remove( z.m_zone );
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Add( z.m_zone );
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}
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m_connClusters = SearchClusters( CSM_CONNECTIVITY_CHECK );
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for( auto& zone : aZones )
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{
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for( PCB_LAYER_ID layer : zone.m_zone->GetLayerSet().Seq() )
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{
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if( zone.m_zone->GetFilledPolysList( layer ).IsEmpty() )
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continue;
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for( const auto& cluster : m_connClusters )
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{
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if( cluster->Contains( zone.m_zone ) && cluster->IsOrphaned() )
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{
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for( auto z : *cluster )
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|
{
|
|
if( z->Parent() == zone.m_zone && z->Layer() == layer )
|
|
{
|
|
zone.m_islands[layer].push_back(
|
|
static_cast<CN_ZONE*>( z )->SubpolyIndex() );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
const CN_CONNECTIVITY_ALGO::CLUSTERS& CN_CONNECTIVITY_ALGO::GetClusters()
|
|
{
|
|
m_ratsnestClusters = SearchClusters( CSM_RATSNEST );
|
|
return m_ratsnestClusters;
|
|
}
|
|
|
|
|
|
void CN_CONNECTIVITY_ALGO::MarkNetAsDirty( int aNet )
|
|
{
|
|
if( aNet < 0 )
|
|
return;
|
|
|
|
if( (int) m_dirtyNets.size() <= aNet )
|
|
{
|
|
int lastNet = m_dirtyNets.size() - 1;
|
|
|
|
if( lastNet < 0 )
|
|
lastNet = 0;
|
|
|
|
m_dirtyNets.resize( aNet + 1 );
|
|
|
|
for( int i = lastNet; i < aNet + 1; i++ )
|
|
m_dirtyNets[i] = true;
|
|
}
|
|
|
|
m_dirtyNets[aNet] = true;
|
|
}
|
|
|
|
|
|
void CN_VISITOR::checkZoneItemConnection( CN_ZONE* aZone, CN_ITEM* aItem )
|
|
{
|
|
if( aZone->Net() != aItem->Net() && !aItem->CanChangeNet() )
|
|
return;
|
|
|
|
if( !aZone->BBox().Intersects( aItem->BBox() ) )
|
|
return;
|
|
|
|
CN_ZONE* zoneItem = static_cast<CN_ZONE*> ( aZone );
|
|
int accuracy = 0;
|
|
|
|
if( aItem->Parent()->Type() == PCB_VIA_T
|
|
|| aItem->Parent()->Type() == PCB_TRACE_T
|
|
|| aItem->Parent()->Type() == PCB_ARC_T )
|
|
accuracy = ( static_cast<TRACK*>( aItem->Parent() )->GetWidth() + 1 ) / 2;
|
|
|
|
for( int i = 0; i < aItem->AnchorCount(); ++i )
|
|
{
|
|
if( zoneItem->ContainsPoint( aItem->GetAnchor( i ), accuracy ) )
|
|
{
|
|
zoneItem->Connect( aItem );
|
|
aItem->Connect( zoneItem );
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
void CN_VISITOR::checkZoneZoneConnection( CN_ZONE* aZoneA, CN_ZONE* aZoneB )
|
|
{
|
|
const auto parentA = static_cast<const ZONE_CONTAINER*>( aZoneA->Parent() );
|
|
const auto parentB = static_cast<const ZONE_CONTAINER*>( aZoneB->Parent() );
|
|
|
|
if( aZoneB == aZoneA || parentA == parentB )
|
|
return;
|
|
|
|
if( aZoneA->Layer() != aZoneB->Layer() )
|
|
return;
|
|
|
|
if( aZoneB->Net() != aZoneA->Net() )
|
|
return; // we only test zones belonging to the same net
|
|
|
|
const BOX2I& boxA = aZoneA->BBox();
|
|
const BOX2I& boxB = aZoneB->BBox();
|
|
|
|
int radiusA = 0;
|
|
int radiusB = 0;
|
|
|
|
if( parentA->GetFilledPolysUseThickness() )
|
|
radiusA = ( parentA->GetMinThickness() + 1 ) / 2;
|
|
|
|
if( parentB->GetFilledPolysUseThickness() )
|
|
radiusB = ( parentB->GetMinThickness() + 1 ) / 2;
|
|
|
|
PCB_LAYER_ID layer = static_cast<PCB_LAYER_ID>( aZoneA->Layer() );
|
|
|
|
const auto& outline = parentA->GetFilledPolysList( layer ).COutline( aZoneA->SubpolyIndex() );
|
|
|
|
for( int i = 0; i < outline.PointCount(); i++ )
|
|
{
|
|
if( !boxB.Contains( outline.CPoint( i ) ) )
|
|
continue;
|
|
|
|
if( aZoneB->ContainsPoint( outline.CPoint( i ), radiusA ) )
|
|
{
|
|
aZoneA->Connect( aZoneB );
|
|
aZoneB->Connect( aZoneA );
|
|
return;
|
|
}
|
|
}
|
|
|
|
const auto& outline2 =
|
|
parentB->GetFilledPolysList( layer ).COutline( aZoneB->SubpolyIndex() );
|
|
|
|
for( int i = 0; i < outline2.PointCount(); i++ )
|
|
{
|
|
if( !boxA.Contains( outline2.CPoint( i ) ) )
|
|
continue;
|
|
|
|
if( aZoneA->ContainsPoint( outline2.CPoint( i ), radiusB ) )
|
|
{
|
|
aZoneA->Connect( aZoneB );
|
|
aZoneB->Connect( aZoneA );
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
bool CN_VISITOR::operator()( CN_ITEM* aCandidate )
|
|
{
|
|
const BOARD_CONNECTED_ITEM* parentA = aCandidate->Parent();
|
|
const BOARD_CONNECTED_ITEM* parentB = m_item->Parent();
|
|
|
|
if( !aCandidate->Valid() || !m_item->Valid() )
|
|
return true;
|
|
|
|
if( parentA == parentB )
|
|
return true;
|
|
|
|
if( !( parentA->GetLayerSet() & parentB->GetLayerSet() ).any() )
|
|
return true;
|
|
|
|
// If both m_item and aCandidate are marked dirty, they will both be searched
|
|
// Since we are reciprocal in our connection, we arbitrarily pick one of the connections
|
|
// to conduct the expensive search
|
|
if( aCandidate->Dirty() && aCandidate < m_item )
|
|
return true;
|
|
|
|
// We should handle zone-zone connection separately
|
|
if ( parentA->Type() == PCB_ZONE_AREA_T && parentB->Type() == PCB_ZONE_AREA_T )
|
|
{
|
|
checkZoneZoneConnection( static_cast<CN_ZONE*>( m_item ),
|
|
static_cast<CN_ZONE*>( aCandidate ) );
|
|
return true;
|
|
}
|
|
|
|
if( parentA->Type() == PCB_ZONE_AREA_T )
|
|
{
|
|
checkZoneItemConnection( static_cast<CN_ZONE*>( aCandidate ), m_item );
|
|
return true;
|
|
}
|
|
|
|
if( parentB->Type() == PCB_ZONE_AREA_T )
|
|
{
|
|
checkZoneItemConnection( static_cast<CN_ZONE*>( m_item ), aCandidate );
|
|
return true;
|
|
}
|
|
|
|
int accuracyA = 0;
|
|
int accuracyB = 0;
|
|
|
|
if( parentA->Type() == PCB_VIA_T
|
|
|| parentA->Type() == PCB_TRACE_T
|
|
|| parentA->Type() == PCB_ARC_T)
|
|
accuracyA = ( static_cast<const TRACK*>( parentA )->GetWidth() + 1 ) / 2;
|
|
|
|
if( parentB->Type() == PCB_VIA_T
|
|
|| parentB->Type() == PCB_TRACE_T
|
|
|| parentB->Type() == PCB_ARC_T )
|
|
accuracyB = ( static_cast<const TRACK*>( parentB )->GetWidth() + 1 ) / 2;
|
|
|
|
// Items do not necessarily have reciprocity as we only check for anchors
|
|
// therefore, we check HitTest both directions A->B & B->A
|
|
for( int i = 0; i < aCandidate->AnchorCount(); ++i )
|
|
{
|
|
if( parentB->HitTest( wxPoint( aCandidate->GetAnchor( i ) ), accuracyA ) )
|
|
{
|
|
m_item->Connect( aCandidate );
|
|
aCandidate->Connect( m_item );
|
|
return true;
|
|
}
|
|
}
|
|
|
|
for( int i = 0; i < m_item->AnchorCount(); ++i )
|
|
{
|
|
if( parentA->HitTest( wxPoint( m_item->GetAnchor( i ) ), accuracyB ) )
|
|
{
|
|
m_item->Connect( aCandidate );
|
|
aCandidate->Connect( m_item );
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
};
|
|
|
|
|
|
void CN_CONNECTIVITY_ALGO::Clear()
|
|
{
|
|
m_ratsnestClusters.clear();
|
|
m_connClusters.clear();
|
|
m_itemMap.clear();
|
|
m_itemList.Clear();
|
|
|
|
}
|
|
|
|
void CN_CONNECTIVITY_ALGO::SetProgressReporter( PROGRESS_REPORTER* aReporter )
|
|
{
|
|
m_progressReporter = aReporter;
|
|
}
|