mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-14 02:03:12 +02:00
e09271ca0e
1) Separate out CONSTRAINT types 2) Filter both source and dest pads/vias for drilled holes when doing hole-to-hole checks. We were checking the items being put into the DRC RTree, but not the items we were scanning. 3) Add hole clearance to Board Setup Constraints panel. Fixes https://gitlab.com/kicad/code/kicad/issues/6546 Fixes https://gitlab.com/kicad/code/kicad/issues/4683
823 lines
28 KiB
C++
823 lines
28 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2020 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <board.h>
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#include <pcb_shape.h>
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#include <pad.h>
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#include <track.h>
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#include <geometry/seg.h>
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#include <geometry/shape_poly_set.h>
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#include <geometry/shape_rect.h>
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#include <geometry/shape_segment.h>
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#include <geometry/shape_null.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_rtree.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <dimension.h>
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/*
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Copper clearance test. Checks all copper items (pads, vias, tracks, drawings, zones) for their electrical clearance.
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Errors generated:
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- DRCE_CLEARANCE
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- DRCE_TRACKS_CROSSING
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- DRCE_ZONES_INTERSECT
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- DRCE_SHORTING_ITEMS
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*/
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class DRC_TEST_PROVIDER_COPPER_CLEARANCE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
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{
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public:
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DRC_TEST_PROVIDER_COPPER_CLEARANCE () :
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DRC_TEST_PROVIDER_CLEARANCE_BASE(),
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m_drcEpsilon( 0 )
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{
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}
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virtual ~DRC_TEST_PROVIDER_COPPER_CLEARANCE()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return "clearance";
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};
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virtual const wxString GetDescription() const override
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{
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return "Tests copper item clearance";
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}
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virtual std::set<DRC_CONSTRAINT_TYPE_T> GetConstraintTypes() const override;
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int GetNumPhases() const override;
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private:
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bool testTrackAgainstItem( TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer,
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BOARD_ITEM* other );
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void testTrackClearances();
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bool testPadAgainstItem( PAD* pad, SHAPE* padShape, PCB_LAYER_ID layer, BOARD_ITEM* other );
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void testPadClearances();
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void testZones();
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void testItemAgainstZones( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer );
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private:
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DRC_RTREE m_copperTree;
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int m_drcEpsilon;
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std::vector<ZONE*> m_zones;
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std::map<ZONE*, std::unique_ptr<DRC_RTREE>> m_zoneTrees;
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};
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run()
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{
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m_board = m_drcEngine->GetBoard();
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DRC_CONSTRAINT worstClearanceConstraint;
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if( m_drcEngine->QueryWorstConstraint( CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
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{
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m_largestClearance = worstClearanceConstraint.GetValue().Min();
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}
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else
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{
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reportAux( "No Clearance constraints found..." );
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return false;
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}
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m_drcEpsilon = m_board->GetDesignSettings().GetDRCEpsilon();
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m_zones.clear();
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for( ZONE* zone : m_board->Zones() )
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{
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if( !zone->GetIsRuleArea() )
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m_zones.push_back( zone );
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}
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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for( ZONE* zone : footprint->Zones() )
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{
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if( !zone->GetIsRuleArea() )
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m_zones.push_back( zone );
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}
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}
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reportAux( "Worst clearance : %d nm", m_largestClearance );
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// This is the number of tests between 2 calls to the progress bar
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size_t delta = 50;
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size_t count = 0;
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size_t ii = 0;
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m_copperTree.clear();
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auto countItems =
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[&]( BOARD_ITEM* item ) -> bool
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{
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++count;
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return true;
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};
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auto addToCopperTree =
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( !reportProgress( ii++, count, delta ) )
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return false;
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if( item->Type() == PCB_FP_TEXT_T && !static_cast<FP_TEXT*>( item )->IsVisible() )
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return true;
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m_copperTree.Insert( item, m_largestClearance );
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return true;
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};
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if( !reportPhase( _( "Gathering copper items..." ) ) )
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return false;
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static const std::vector<KICAD_T> itemTypes = {
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PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T, PCB_SHAPE_T, PCB_FP_SHAPE_T,
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PCB_TEXT_T, PCB_FP_TEXT_T, PCB_DIMENSION_T, PCB_DIM_ALIGNED_T, PCB_DIM_LEADER_T,
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PCB_DIM_CENTER_T, PCB_DIM_ORTHOGONAL_T
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};
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forEachGeometryItem( itemTypes, LSET::AllCuMask(), countItems );
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forEachGeometryItem( itemTypes, LSET::AllCuMask(), addToCopperTree );
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if( !reportPhase( _( "Tessellating copper zones..." ) ) )
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return false;
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delta = 5;
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ii = 0;
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m_zoneTrees.clear();
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for( ZONE* zone : m_zones )
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{
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if( !reportProgress( ii++, m_zones.size(), delta ) )
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break;
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zone->CacheBoundingBox();
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m_zoneTrees[ zone ] = std::make_unique<DRC_RTREE>();
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for( int layer : zone->GetLayerSet().Seq() )
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{
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if( IsCopperLayer( layer ) )
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m_zoneTrees[ zone ]->Insert( zone, layer );
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}
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}
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reportAux( "Testing %d copper items and %d zones...", count, m_zones.size() );
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if( !reportPhase( _( "Checking track & via clearances..." ) ) )
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return false;
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testTrackClearances();
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if( !reportPhase( _( "Checking pad clearances..." ) ) )
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return false;
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testPadClearances();
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if( !reportPhase( _( "Checking copper zone clearances..." ) ) )
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return false;
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testZones();
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reportRuleStatistics();
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return true;
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}
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static std::shared_ptr<SHAPE> getShape( BOARD_ITEM* aItem, PCB_LAYER_ID aLayer )
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{
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if( aItem->Type() == PCB_PAD_T && !static_cast<PAD*>( aItem )->FlashLayer( aLayer ) )
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{
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PAD* aPad = static_cast<PAD*>( aItem );
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if( aPad->GetAttribute() == PAD_ATTRIB_PTH )
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{
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BOARD_DESIGN_SETTINGS& bds = aPad->GetBoard()->GetDesignSettings();
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// Note: drill size represents finish size, which means the actual holes size is the
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// plating thickness larger.
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auto hole = static_cast<SHAPE_SEGMENT*>( aPad->GetEffectiveHoleShape()->Clone() );
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hole->SetWidth( hole->GetWidth() + bds.GetHolePlatingThickness() );
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return std::make_shared<SHAPE_SEGMENT>( *hole );
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}
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return std::make_shared<SHAPE_NULL>();
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}
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return aItem->GetEffectiveShape( aLayer );
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}
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static bool isNetTie( BOARD_ITEM* aItem )
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{
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if( aItem->GetParent() && aItem->GetParent()->Type() == PCB_FOOTPRINT_T )
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return static_cast<FOOTPRINT*>( aItem->GetParent() )->IsNetTie();
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return false;
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}
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHAPE* trackShape,
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PCB_LAYER_ID layer,
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BOARD_ITEM* other )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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return false;
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auto constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, track, other,
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layer );
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int minClearance = constraint.GetValue().Min();
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int actual;
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VECTOR2I pos;
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accountCheck( constraint );
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// Special processing for track:track intersections
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if( track->Type() == PCB_TRACE_T && other->Type() == PCB_TRACE_T )
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{
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SEG trackSeg( track->GetStart(), track->GetEnd() );
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SEG otherSeg( track->GetStart(), track->GetEnd() );
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if( OPT_VECTOR2I intersection = trackSeg.Intersect( otherSeg ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACKS_CROSSING );
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drcItem->SetItems( track, other );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, (wxPoint) intersection.get() );
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return true;
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}
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}
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std::shared_ptr<SHAPE> otherShape = getShape( other, layer );
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if( trackShape->Collide( otherShape.get(), minClearance - m_drcEpsilon, &actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
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m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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MessageTextFromValue( userUnits(), minClearance ),
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MessageTextFromValue( userUnits(), actual ) );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
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drce->SetItems( track, other );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, (wxPoint) pos );
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if( !m_drcEngine->GetReportAllTrackErrors() )
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return false;
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}
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return true;
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}
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void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZones( BOARD_ITEM* aItem,
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PCB_LAYER_ID aLayer )
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{
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for( ZONE* zone : m_zones )
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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break;
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if( !zone->GetLayerSet().test( aLayer ) )
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continue;
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if( zone->GetNetCode() && aItem->IsConnected() )
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{
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if( zone->GetNetCode() == static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() )
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continue;
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}
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if( aItem->GetBoundingBox().Intersects( zone->GetCachedBoundingBox() ) )
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{
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auto constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, aItem, zone,
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aLayer );
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int clearance = constraint.GetValue().Min();
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int actual;
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VECTOR2I pos;
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DRC_RTREE* zoneTree = m_zoneTrees[ zone ].get();
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EDA_RECT itemBBox = aItem->GetBoundingBox();
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std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer );
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if( aItem->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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if( !pad->FlashLayer( aLayer ) )
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{
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if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
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continue;
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const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape();
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int size = hole->GetWidth();
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// Note: drill size represents finish size, which means the actual hole
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// size is the plating thickness larger.
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if( pad->GetAttribute() == PAD_ATTRIB_PTH )
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size += m_board->GetDesignSettings().GetHolePlatingThickness();
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itemShape = std::make_shared<SHAPE_SEGMENT>( hole->GetSeg(), size );
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}
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}
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if( zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
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clearance - m_drcEpsilon,
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&actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
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m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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MessageTextFromValue( userUnits(), clearance ),
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MessageTextFromValue( userUnits(), actual ) );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
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drce->SetItems( aItem, zone );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, (wxPoint) pos );
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}
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}
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}
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}
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void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
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{
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// This is the number of tests between 2 calls to the progress bar
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const int delta = 25;
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int ii = 0;
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reportAux( "Testing %d tracks & vias...", m_board->Tracks().size() );
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std::map< std::pair<BOARD_ITEM*, BOARD_ITEM*>, int> checkedPairs;
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for( TRACK* track : m_board->Tracks() )
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{
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if( !reportProgress( ii++, m_board->Tracks().size(), delta ) )
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break;
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for( PCB_LAYER_ID layer : track->GetLayerSet().Seq() )
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{
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std::shared_ptr<SHAPE> trackShape = track->GetEffectiveShape( layer );
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m_copperTree.QueryColliding( track, layer, layer,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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// It would really be better to know what particular nets a nettie
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// should allow, but for now it is what it is.
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if( isNetTie( other ) )
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return false;
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auto otherCItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( other );
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if( otherCItem && otherCItem->GetNetCode() == track->GetNetCode() )
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return false;
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BOARD_ITEM* a = track;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions
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// (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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if( checkedPairs.count( { a, b } ) )
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{
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return false;
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}
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else
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{
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checkedPairs[ { a, b } ] = 1;
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return true;
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}
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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return testTrackAgainstItem( track, trackShape.get(), layer, other );
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},
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m_largestClearance );
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testItemAgainstZones( track, layer );
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}
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}
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}
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* padShape,
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PCB_LAYER_ID layer,
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BOARD_ITEM* other )
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{
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testShorting = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
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bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
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// Graphic items are allowed to act as net-ties within their own footprint
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if( other->Type() == PCB_FP_SHAPE_T && pad->GetParent() == other->GetParent() )
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testClearance = false;
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if( !testClearance && !testShorting && !testHoles )
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return false;
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std::shared_ptr<SHAPE> otherShape = getShape( other, layer );
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DRC_CONSTRAINT constraint;
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int clearance;
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int actual;
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VECTOR2I pos;
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if( other->Type() == PCB_PAD_T )
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{
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auto otherPad = static_cast<PAD*>( other );
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// If pads are equivalent (ie: from the same footprint with the same pad number)...
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if( pad->SameLogicalPadAs( otherPad ) )
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{
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// ...and have nets, then they must be the same net
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if( pad->GetNetCode() && otherPad->GetNetCode()
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&& pad->GetNetCode() != otherPad->GetNetCode()
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&& testShorting )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
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m_msg.Printf( _( "(nets %s and %s)" ),
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pad->GetNetname(),
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otherPad->GetNetname() );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
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drce->SetItems( pad, otherPad );
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reportViolation( drce, otherPad->GetPosition() );
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}
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return true;
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}
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if( testHoles )
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{
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if( ( pad->FlashLayer( layer ) && otherPad->GetDrillSize().x )
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|| ( pad->GetDrillSize().x && otherPad->FlashLayer( layer ) ) )
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{
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constraint = m_drcEngine->EvalRulesForItems( HOLE_CLEARANCE_CONSTRAINT, pad,
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otherPad );
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clearance = constraint.GetValue().Min();
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accountCheck( constraint.GetParentRule() );
|
|
|
|
if( padShape->Collide( otherShape.get(), clearance - m_drcEpsilon, &actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
|
|
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
MessageTextFromValue( userUnits(), clearance ),
|
|
MessageTextFromValue( userUnits(), actual ) );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
|
|
drce->SetItems( pad, other );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, (wxPoint) pos );
|
|
}
|
|
}
|
|
}
|
|
|
|
// Pads of the same (defined) net get a waiver on clearance tests
|
|
if( pad->GetNetCode() && otherPad->GetNetCode() == pad->GetNetCode() )
|
|
testClearance = false;
|
|
}
|
|
|
|
if( testClearance )
|
|
{
|
|
constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, pad, other, layer );
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
accountCheck( constraint );
|
|
|
|
if( padShape->Collide( otherShape.get(), clearance - m_drcEpsilon, &actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
|
|
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
MessageTextFromValue( userUnits(), clearance ),
|
|
MessageTextFromValue( userUnits(), actual ) );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
|
|
drce->SetItems( pad, other );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, (wxPoint) pos );
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
|
|
{
|
|
const int delta = 25; // This is the number of tests between 2 calls to the progress bar
|
|
|
|
size_t count = 0;
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
count += footprint->Pads().size();
|
|
|
|
reportAux( "Testing %d pads...", count );
|
|
|
|
int ii = 0;
|
|
std::map< std::pair<BOARD_ITEM*, BOARD_ITEM*>, int> checkedPairs;
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
if( !reportProgress( ii++, count, delta ) )
|
|
break;
|
|
|
|
for( PCB_LAYER_ID layer : pad->GetLayerSet().Seq() )
|
|
{
|
|
std::shared_ptr<SHAPE> padShape = getShape( pad, layer );
|
|
|
|
m_copperTree.QueryColliding( pad, layer, layer,
|
|
// Filter:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
BOARD_ITEM* a = pad;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both directions
|
|
// (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
if( checkedPairs.count( { a, b } ) )
|
|
{
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
checkedPairs[ { a, b } ] = 1;
|
|
return true;
|
|
}
|
|
},
|
|
// Visitor
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
return testPadAgainstItem( pad, padShape.get(), layer, other );
|
|
},
|
|
m_largestClearance );
|
|
|
|
testItemAgainstZones( pad, layer );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZones()
|
|
{
|
|
const int delta = 50; // This is the number of tests between 2 calls to the progress bar
|
|
|
|
SHAPE_POLY_SET buffer;
|
|
SHAPE_POLY_SET* boardOutline = nullptr;
|
|
|
|
if( m_board->GetBoardPolygonOutlines( buffer ) )
|
|
boardOutline = &buffer;
|
|
|
|
for( int layer_id = F_Cu; layer_id <= B_Cu; ++layer_id )
|
|
{
|
|
PCB_LAYER_ID layer = static_cast<PCB_LAYER_ID>( layer_id );
|
|
std::vector<SHAPE_POLY_SET> smoothed_polys;
|
|
smoothed_polys.resize( m_zones.size() );
|
|
|
|
// Skip over layers not used on the current board
|
|
if( !m_board->IsLayerEnabled( layer ) )
|
|
continue;
|
|
|
|
for( size_t ii = 0; ii < m_zones.size(); ii++ )
|
|
{
|
|
if( m_zones[ii]->IsOnLayer( layer ) )
|
|
m_zones[ii]->BuildSmoothedPoly( smoothed_polys[ii], layer, boardOutline );
|
|
}
|
|
|
|
// iterate through all areas
|
|
for( size_t ia = 0; ia < m_zones.size(); ia++ )
|
|
{
|
|
if( !reportProgress( layer_id * m_zones.size() + ia, B_Cu * m_zones.size(), delta ) )
|
|
break;
|
|
|
|
ZONE* zoneRef = m_zones[ia];
|
|
|
|
if( !zoneRef->IsOnLayer( layer ) )
|
|
continue;
|
|
|
|
// If we are testing a single zone, then iterate through all other zones
|
|
// Otherwise, we have already tested the zone combination
|
|
for( size_t ia2 = ia + 1; ia2 < m_zones.size(); ia2++ )
|
|
{
|
|
ZONE* zoneToTest = m_zones[ia2];
|
|
|
|
if( zoneRef == zoneToTest )
|
|
continue;
|
|
|
|
// test for same layer
|
|
if( !zoneToTest->IsOnLayer( layer ) )
|
|
continue;
|
|
|
|
// Test for same net
|
|
if( zoneRef->GetNetCode() == zoneToTest->GetNetCode() && zoneRef->GetNetCode() >= 0 )
|
|
continue;
|
|
|
|
// test for different priorities
|
|
if( zoneRef->GetPriority() != zoneToTest->GetPriority() )
|
|
continue;
|
|
|
|
// test for different types
|
|
if( zoneRef->GetIsRuleArea() != zoneToTest->GetIsRuleArea() )
|
|
continue;
|
|
|
|
// Examine a candidate zone: compare zoneToTest to zoneRef
|
|
|
|
// Get clearance used in zone to zone test.
|
|
auto constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, zoneRef,
|
|
zoneToTest );
|
|
int zone2zoneClearance = constraint.GetValue().Min();
|
|
|
|
accountCheck( constraint );
|
|
|
|
// Keepout areas have no clearance, so set zone2zoneClearance to 1
|
|
// ( zone2zoneClearance = 0 can create problems in test functions)
|
|
if( zoneRef->GetIsRuleArea() ) // fixme: really?
|
|
zone2zoneClearance = 1;
|
|
|
|
// test for some corners of zoneRef inside zoneToTest
|
|
for( auto iterator = smoothed_polys[ia].IterateWithHoles(); iterator; iterator++ )
|
|
{
|
|
VECTOR2I currentVertex = *iterator;
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
if( smoothed_polys[ia2].Contains( currentVertex ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
drce->SetItems( zoneRef, zoneToTest );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pt );
|
|
}
|
|
}
|
|
|
|
// test for some corners of zoneToTest inside zoneRef
|
|
for( auto iterator = smoothed_polys[ia2].IterateWithHoles(); iterator; iterator++ )
|
|
{
|
|
VECTOR2I currentVertex = *iterator;
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
if( smoothed_polys[ia].Contains( currentVertex ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
drce->SetItems( zoneToTest, zoneRef );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pt );
|
|
}
|
|
}
|
|
|
|
// Iterate through all the segments of refSmoothedPoly
|
|
std::map<wxPoint, int> conflictPoints;
|
|
|
|
for( auto refIt = smoothed_polys[ia].IterateSegmentsWithHoles(); refIt; refIt++ )
|
|
{
|
|
// Build ref segment
|
|
SEG refSegment = *refIt;
|
|
|
|
// Iterate through all the segments in smoothed_polys[ia2]
|
|
for( auto testIt = smoothed_polys[ia2].IterateSegmentsWithHoles(); testIt; testIt++ )
|
|
{
|
|
// Build test segment
|
|
SEG testSegment = *testIt;
|
|
wxPoint pt;
|
|
|
|
int ax1, ay1, ax2, ay2;
|
|
ax1 = refSegment.A.x;
|
|
ay1 = refSegment.A.y;
|
|
ax2 = refSegment.B.x;
|
|
ay2 = refSegment.B.y;
|
|
|
|
int bx1, by1, bx2, by2;
|
|
bx1 = testSegment.A.x;
|
|
by1 = testSegment.A.y;
|
|
bx2 = testSegment.B.x;
|
|
by2 = testSegment.B.y;
|
|
|
|
int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2,
|
|
0,
|
|
ax1, ay1, ax2, ay2,
|
|
0,
|
|
zone2zoneClearance,
|
|
&pt.x, &pt.y );
|
|
|
|
if( d < zone2zoneClearance )
|
|
{
|
|
if( conflictPoints.count( pt ) )
|
|
conflictPoints[ pt ] = std::min( conflictPoints[ pt ], d );
|
|
else
|
|
conflictPoints[ pt ] = d;
|
|
}
|
|
}
|
|
}
|
|
|
|
for( const std::pair<const wxPoint, int>& conflict : conflictPoints )
|
|
{
|
|
int actual = conflict.second;
|
|
std::shared_ptr<DRC_ITEM> drce;
|
|
|
|
if( actual <= 0 )
|
|
{
|
|
drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
}
|
|
else
|
|
{
|
|
drce = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
|
|
m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
MessageTextFromValue( userUnits(), zone2zoneClearance ),
|
|
MessageTextFromValue( userUnits(), conflict.second ) );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
|
|
}
|
|
|
|
drce->SetItems( zoneRef, zoneToTest );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, conflict.first );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
int DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetNumPhases() const
|
|
{
|
|
return 5;
|
|
}
|
|
|
|
|
|
std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_COPPER_CLEARANCE::GetConstraintTypes() const
|
|
{
|
|
return { CLEARANCE_CONSTRAINT, HOLE_CLEARANCE_CONSTRAINT };
|
|
}
|
|
|
|
|
|
namespace detail
|
|
{
|
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_COPPER_CLEARANCE> dummy;
|
|
}
|