mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-14 02:03:12 +02:00
b47f172e57
Its purpose is to initialize the top and the bottom copper layers connected by this via. So only copper layers in LSET must be analyzed.
597 lines
19 KiB
C++
597 lines
19 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com
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* Copyright (C) 1992-2023 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @brief A single base class (PCB_TRACK) represents both tracks and vias, with subclasses
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* for curved tracks (PCB_ARC) and vias (PCB_VIA). All told there are three KICAD_Ts:
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* PCB_TRACK_T, PCB_ARC_T, and PCB_VIA_T.
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*
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* For vias there is a further VIATYPE which indicates THROUGH, BLIND_BURIED, or MICROVIA,
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* which are supported by the synthetic KICAD_Ts PCB_LOCATE_STDVIA_T, PCB_LOCATE_BBVIA_T, and
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* PCB_LOCATE_UVIA_T.
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*/
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#ifndef CLASS_TRACK_H
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#define CLASS_TRACK_H
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#include <mutex>
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#include <array>
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#include <board_connected_item.h>
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#include <base_units.h>
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#include <geometry/shape_segment.h>
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#include <core/minoptmax.h>
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#include <core/arraydim.h>
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class PCB_TRACK;
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class PCB_VIA;
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class PAD;
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class MSG_PANEL_ITEM;
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class SHAPE_POLY_SET;
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class SHAPE_ARC;
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// Flag used in locate routines (from which endpoint work)
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enum ENDPOINT_T : int
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{
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ENDPOINT_START = 0,
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ENDPOINT_END = 1
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};
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// Note that this enum must be synchronized to GAL_LAYER_ID
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enum class VIATYPE : int
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{
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THROUGH = 3, /* Always a through hole via */
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BLIND_BURIED = 2, /* this via can be on internal layers */
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MICROVIA = 1, /* this via which connect from an external layer
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* to the near neighbor internal layer */
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NOT_DEFINED = 0 /* not yet used */
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};
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#define UNDEFINED_DRILL_DIAMETER -1 //< Undefined via drill diameter.
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// Used for tracks and vias for algorithmic safety, not to enforce constraints
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#define GEOMETRY_MIN_SIZE (int) ( 0.001 * pcbIUScale.IU_PER_MM )
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class PCB_TRACK : public BOARD_CONNECTED_ITEM
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{
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public:
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static inline bool ClassOf( const EDA_ITEM* aItem )
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{
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return aItem && PCB_TRACE_T == aItem->Type();
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}
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PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype = PCB_TRACE_T );
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// Do not create a copy constructor. The one generated by the compiler is adequate.
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void Move( const VECTOR2I& aMoveVector ) override
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{
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m_Start += aMoveVector;
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m_End += aMoveVector;
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}
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void Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle ) override;
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virtual void Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis );
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void Flip( const VECTOR2I& aCentre, bool aFlipLeftRight ) override;
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void SetPosition( const VECTOR2I& aPos ) override { m_Start = aPos; }
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VECTOR2I GetPosition() const override { return m_Start; }
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const VECTOR2I GetFocusPosition() const override { return ( m_Start + m_End ) / 2; }
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void SetWidth( int aWidth ) { m_Width = aWidth; }
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int GetWidth() const { return m_Width; }
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void SetEnd( const VECTOR2I& aEnd ) { m_End = aEnd; }
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const VECTOR2I& GetEnd() const { return m_End; }
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void SetStart( const VECTOR2I& aStart ) { m_Start = aStart; }
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const VECTOR2I& GetStart() const { return m_Start; }
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void SetEndX( int aX ) { m_End.x = aX; }
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void SetEndY( int aY ) { m_End.y = aY; }
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int GetEndX() const { return m_End.x; }
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int GetEndY() const { return m_End.y; }
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/// Return the selected endpoint (start or end)
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const VECTOR2I& GetEndPoint( ENDPOINT_T aEndPoint ) const
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{
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if( aEndPoint == ENDPOINT_START )
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return m_Start;
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else
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return m_End;
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}
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// Virtual function
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const BOX2I GetBoundingBox() const override;
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/**
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* Get the length of the track using the hypotenuse calculation.
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*
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* @return the length of the track.
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*/
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virtual double GetLength() const;
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/**
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* Convert the track shape to a closed polygon.
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*
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* Circles (vias) and arcs (ends of tracks) are approximated by segments.
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*
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* @param aBuffer is a buffer to store the polygon
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* @param aClearance is the clearance around the pad
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* @param aError is the maximum deviation from true circle
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* @param ignoreLineWidth is used for edge cut items where the line width is only for
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* visualization
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*/
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void TransformShapeToPolygon( SHAPE_POLY_SET& aBuffer, PCB_LAYER_ID aLayer, int aClearance,
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int aError, ERROR_LOC aErrorLoc,
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bool ignoreLineWidth = false ) const override;
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// @copydoc BOARD_ITEM::GetEffectiveShape
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std::shared_ptr<SHAPE> GetEffectiveShape( PCB_LAYER_ID aLayer = UNDEFINED_LAYER,
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FLASHING aFlash = FLASHING::DEFAULT ) const override;
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/**
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* Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if
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* point if near (dist = min_dist) end point,STARTPOINT|ENDPOINT if point if near
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* (dist = min_dist) both ends, or 0 if none of the above.
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*
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* If min_dist < 0: min_dist = track_width/2
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*/
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EDA_ITEM_FLAGS IsPointOnEnds( const VECTOR2I& point, int min_dist = 0 ) const;
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/**
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* Return true if segment length is zero.
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*/
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bool IsNull() const
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{
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return ( Type() == PCB_VIA_T ) || ( m_Start == m_End );
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}
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void GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList ) override;
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wxString GetFriendlyName() const override;
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INSPECT_RESULT Visit( INSPECTOR inspector, void* testData,
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const std::vector<KICAD_T>& aScanTypes ) override;
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bool HitTest( const VECTOR2I& aPosition, int aAccuracy = 0 ) const override;
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bool HitTest( const BOX2I& aRect, bool aContained, int aAccuracy = 0 ) const override;
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bool ApproxCollinear( const PCB_TRACK& aTrack );
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wxString GetClass() const override
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{
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return wxT( "PCB_TRACK" );
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}
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/**
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* Return any local clearance overrides set in the "classic" (ie: pre-rule) system.
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*
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* @param aSource [out] optionally reports the source as a user-readable string
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* @return int - the clearance in internal units.
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*/
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int GetLocalClearance( wxString* aSource ) const override;
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MINOPTMAX<int> GetWidthConstraint( wxString* aSource = nullptr ) const;
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wxString GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const override;
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BITMAPS GetMenuImage() const override;
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virtual EDA_ITEM* Clone() const override;
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virtual void ViewGetLayers( int aLayers[], int& aCount ) const override;
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double ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const override;
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const BOX2I ViewBBox() const override;
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/**
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* @return true because a track or a via is always on a copper layer.
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*/
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bool IsOnCopperLayer() const override
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{
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return true;
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}
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/**
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* Get last used LOD for the track net name.
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*
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* @return LOD from ViewGetLOD()
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*/
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double GetCachedLOD()
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{
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return m_CachedLOD;
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}
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/**
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* Set the cached LOD.
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*
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* @param aLOD value from ViewGetLOD() or 0.0 to always display.
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*/
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void SetCachedLOD( double aLOD )
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{
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m_CachedLOD = aLOD;
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}
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/**
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* Get last used zoom scale for the track net name.
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*
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* @return scale from GetScale()
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*/
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double GetCachedScale()
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{
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return m_CachedScale;
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}
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/**
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* Set the cached scale.
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*
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* @param aScale value from GetScale()
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*/
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void SetCachedScale( double aScale )
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{
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m_CachedScale = aScale;
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}
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struct cmp_tracks
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{
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bool operator()( const PCB_TRACK* aFirst, const PCB_TRACK* aSecond ) const;
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};
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#if defined (DEBUG)
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virtual void Show( int nestLevel, std::ostream& os ) const override { ShowDummy( os ); }
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#endif
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protected:
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virtual void swapData( BOARD_ITEM* aImage ) override;
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void GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame,
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std::vector<MSG_PANEL_ITEM>& aList ) const;
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protected:
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int m_Width; ///< Thickness of track, or via diameter
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VECTOR2I m_Start; ///< Line start point
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VECTOR2I m_End; ///< Line end point
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double m_CachedLOD; ///< Last LOD used to draw this track's net
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double m_CachedScale; ///< Last zoom scale used to draw this track's net.
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};
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class PCB_ARC : public PCB_TRACK
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{
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public:
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PCB_ARC( BOARD_ITEM* aParent ) :
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PCB_TRACK( aParent, PCB_ARC_T )
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{ }
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PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc );
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static inline bool ClassOf( const EDA_ITEM *aItem )
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{
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return aItem && PCB_ARC_T == aItem->Type();
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}
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virtual void Move( const VECTOR2I& aMoveVector ) override
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{
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m_Start += aMoveVector;
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m_Mid += aMoveVector;
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m_End += aMoveVector;
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}
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void Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle ) override;
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void Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis ) override;
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void Flip( const VECTOR2I& aCentre, bool aFlipLeftRight ) override;
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void SetMid( const VECTOR2I& aMid ) { m_Mid = aMid; }
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const VECTOR2I& GetMid() const { return m_Mid; }
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void SetPosition( const VECTOR2I& aPos ) override { m_Start = aPos; }
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virtual VECTOR2I GetPosition() const override;
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virtual VECTOR2I GetCenter() const override { return GetPosition(); }
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double GetRadius() const;
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EDA_ANGLE GetAngle() const;
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EDA_ANGLE GetArcAngleStart() const;
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EDA_ANGLE GetArcAngleEnd() const; // Called by Python; ignore CLion's claim that it's unused
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virtual bool HitTest( const VECTOR2I& aPosition, int aAccuracy = 0 ) const override;
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virtual bool HitTest( const BOX2I& aRect, bool aContained = true,
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int aAccuracy = 0 ) const override;
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bool IsCCW() const;
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wxString GetClass() const override
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{
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return wxT( "PCB_ARC" );
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}
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// @copydoc BOARD_ITEM::GetEffectiveShape
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std::shared_ptr<SHAPE> GetEffectiveShape( PCB_LAYER_ID aLayer = UNDEFINED_LAYER,
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FLASHING aFlash = FLASHING::DEFAULT ) const override;
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/**
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* Return the length of the arc track.
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*
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* @return double - the length of the track
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*/
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virtual double GetLength() const override
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{
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return GetRadius() * std::abs( GetAngle().AsRadians() );
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}
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EDA_ITEM* Clone() const override;
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protected:
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virtual void swapData( BOARD_ITEM* aImage ) override;
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private:
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VECTOR2I m_Mid; ///< Arc mid point, halfway between start and end
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};
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class PCB_VIA : public PCB_TRACK
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{
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public:
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PCB_VIA( BOARD_ITEM* aParent );
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static inline bool ClassOf( const EDA_ITEM *aItem )
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{
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return aItem && PCB_VIA_T == aItem->Type();
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}
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PCB_VIA( const PCB_VIA& aOther );
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PCB_VIA& operator=( const PCB_VIA &aOther );
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bool IsType( const std::vector<KICAD_T>& aScanTypes ) const override
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{
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if( BOARD_CONNECTED_ITEM::IsType( aScanTypes ) )
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return true;
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for( KICAD_T scanType : aScanTypes )
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{
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if( scanType == PCB_LOCATE_STDVIA_T && m_viaType == VIATYPE::THROUGH )
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return true;
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else if( scanType == PCB_LOCATE_UVIA_T && m_viaType == VIATYPE::MICROVIA )
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return true;
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else if( scanType == PCB_LOCATE_BBVIA_T && m_viaType == VIATYPE::BLIND_BURIED )
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return true;
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}
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return false;
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}
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VIATYPE GetViaType() const { return m_viaType; }
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void SetViaType( VIATYPE aViaType ) { m_viaType = aViaType; }
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bool HasHole() const override
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{
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return true;
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}
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std::shared_ptr<SHAPE_SEGMENT> GetEffectiveHoleShape() const override;
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bool IsTented() const override;
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int GetSolderMaskExpansion() const;
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bool IsOnLayer( PCB_LAYER_ID aLayer, bool aIncludeCourtyards = false ) const override;
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virtual LSET GetLayerSet() const override;
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/**
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* Note SetLayerSet() initialize the first and last copper layers connected by the via.
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* So currently SetLayerSet ignore non copper layers
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*/
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virtual void SetLayerSet( LSET aLayers ) override;
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/**
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* For a via m_layer contains the top layer, the other layer is in m_bottomLayer/
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*
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* @param aTopLayer is the first layer connected by the via.
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* @param aBottomLayer is last layer connected by the via.
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*/
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void SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer );
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void SetBottomLayer( PCB_LAYER_ID aLayer );
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void SetTopLayer( PCB_LAYER_ID aLayer );
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/**
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* Return the 2 layers used by the via (the via actually uses all layers between these
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* 2 layers)
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*
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* @param[out] top_layer is storage for the first layer of the via (can be null).
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* @param[out] bottom_layer is storage for the last layer of the via(can be null).
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*/
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void LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const;
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PCB_LAYER_ID TopLayer() const;
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PCB_LAYER_ID BottomLayer() const;
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/**
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* Check so that the layers are correct depending on the type of via, and
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* so that the top actually is on top.
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*/
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void SanitizeLayers();
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VECTOR2I GetPosition() const override { return m_Start; }
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void SetPosition( const VECTOR2I& aPoint ) override { m_Start = aPoint; m_End = aPoint; }
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void GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList ) override;
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bool HitTest( const VECTOR2I& aPosition, int aAccuracy = 0 ) const override;
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bool HitTest( const BOX2I& aRect, bool aContained, int aAccuracy = 0 ) const override;
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wxString GetClass() const override
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{
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return wxT( "PCB_VIA" );
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}
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wxString GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const override;
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BITMAPS GetMenuImage() const override;
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EDA_ITEM* Clone() const override;
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void ViewGetLayers( int aLayers[], int& aCount ) const override;
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double ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const override;
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void Flip( const VECTOR2I& aCentre, bool aFlipLeftRight ) override;
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#if defined (DEBUG)
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void Show( int nestLevel, std::ostream& os ) const override { ShowDummy( os ); }
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#endif
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int GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const;
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/**
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* Sets the unconnected removal property. If true, the copper is removed on zone fill
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* or when specifically requested when the via is not connected on a layer.
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*/
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void SetRemoveUnconnected( bool aSet ) { m_removeUnconnectedLayer = aSet; }
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bool GetRemoveUnconnected() const { return m_removeUnconnectedLayer; }
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/**
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* Sets whether we keep the start and end annular rings even if they are not connected
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*/
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void SetKeepStartEnd( bool aSet ) { m_keepStartEndLayer = aSet; }
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bool GetKeepStartEnd() const { return m_keepStartEndLayer; }
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bool ConditionallyFlashed( PCB_LAYER_ID aLayer ) const
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{
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if( !m_removeUnconnectedLayer )
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return false;
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if( m_keepStartEndLayer && ( aLayer == m_layer || aLayer == m_bottomLayer ) )
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return false;
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return true;
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}
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/**
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* Check to see whether the via should have a pad on the specific layer.
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*
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* @param aLayer Layer to check for connectivity
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* @return true if connected by pad or track (or optionally zone)
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*/
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bool FlashLayer( int aLayer ) const;
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|
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/**
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* Check to see if the via is present on any of the layers in the set.
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*
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* @param aLayers is the set of layers to check the via against.
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* @return true if connected by pad or track (or optionally zone) on any of the associated
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* layers.
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|
*/
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bool FlashLayer( LSET aLayers ) const;
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|
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/**
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* Set the drill value for vias.
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*
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* @param aDrill is the new drill diameter
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|
*/
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|
void SetDrill( int aDrill ) { m_drill = aDrill; }
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|
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|
/**
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* Return the local drill setting for this PCB_VIA.
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|
*
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* @note Use GetDrillValue() to get the calculated value.
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|
*/
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int GetDrill() const { return m_drill; }
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|
|
|
/**
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|
* Calculate the drill value for vias (m-Drill if > 0, or default drill value for the board.
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|
*
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|
* @return the calculated drill value.
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|
*/
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|
int GetDrillValue() const;
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|
|
|
/**
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|
* Set the drill value for vias to the default value #UNDEFINED_DRILL_DIAMETER.
|
|
*/
|
|
void SetDrillDefault() { m_drill = UNDEFINED_DRILL_DIAMETER; }
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|
|
|
/**
|
|
* Check if the via is a free via (as opposed to one created on a track by the router).
|
|
*
|
|
* Free vias don't have their nets automatically updated by the connectivity algorithm.
|
|
*
|
|
* @return true if the via is a free via
|
|
*/
|
|
bool GetIsFree() const { return m_isFree; }
|
|
void SetIsFree( bool aFree = true ) { m_isFree = aFree; }
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|
|
|
// @copydoc BOARD_ITEM::GetEffectiveShape
|
|
std::shared_ptr<SHAPE> GetEffectiveShape( PCB_LAYER_ID aLayer = UNDEFINED_LAYER,
|
|
FLASHING aFlash = FLASHING::DEFAULT ) const override;
|
|
|
|
void ClearZoneLayerOverrides()
|
|
{
|
|
m_zoneLayerOverrides.fill( ZLO_NONE );
|
|
}
|
|
|
|
const ZONE_LAYER_OVERRIDE& GetZoneLayerOverride( PCB_LAYER_ID aLayer ) const
|
|
{
|
|
return m_zoneLayerOverrides.at( aLayer );
|
|
}
|
|
|
|
void SetZoneLayerOverride( PCB_LAYER_ID aLayer, ZONE_LAYER_OVERRIDE aOverride )
|
|
{
|
|
std::unique_lock<std::mutex> cacheLock( m_zoneLayerOverridesMutex );
|
|
m_zoneLayerOverrides.at( aLayer ) = aOverride;
|
|
}
|
|
|
|
protected:
|
|
void swapData( BOARD_ITEM* aImage ) override;
|
|
|
|
wxString layerMaskDescribe() const override;
|
|
|
|
private:
|
|
/// The bottom layer of the via (the top layer is in m_layer)
|
|
PCB_LAYER_ID m_bottomLayer;
|
|
|
|
VIATYPE m_viaType; ///< through, blind/buried or micro
|
|
|
|
int m_drill; ///< for vias: via drill (- 1 for default value)
|
|
|
|
bool m_removeUnconnectedLayer; ///< Remove annular rings on unconnected layers
|
|
bool m_keepStartEndLayer; ///< Keep the start and end annular rings
|
|
bool m_isFree; ///< "Free" vias don't get their nets auto-updated
|
|
|
|
std::mutex m_zoneLayerOverridesMutex;
|
|
std::array<ZONE_LAYER_OVERRIDE, MAX_CU_LAYERS> m_zoneLayerOverrides;
|
|
};
|
|
|
|
|
|
#endif // CLASS_TRACK_H
|