mirror of
https://gitlab.com/kicad/code/kicad.git
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314 lines
11 KiB
C++
314 lines
11 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright The KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <atomic>
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#include <common.h>
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#include <board_design_settings.h>
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#include <drc/drc_rtree.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <pad.h>
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#include <progress_reporter.h>
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#include <thread_pool.h>
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#include <zone.h>
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#include <pcb_track.h>
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#include <mutex>
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/*
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"Disallow" test. Goes through all items, matching types/conditions drop errors.
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Errors generated:
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- DRCE_ALLOWED_ITEMS
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- DRCE_TEXT_ON_EDGECUTS
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*/
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class DRC_TEST_PROVIDER_DISALLOW : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_DISALLOW()
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{}
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virtual ~DRC_TEST_PROVIDER_DISALLOW() = default;
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virtual bool Run() override;
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virtual const wxString GetName() const override { return wxT( "disallow" ); };
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};
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bool DRC_TEST_PROVIDER_DISALLOW::Run()
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{
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if( !reportPhase( _( "Checking keepouts & disallow constraints..." ) ) )
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return false; // DRC cancelled
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BOARD* board = m_drcEngine->GetBoard();
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int epsilon = board->GetDesignSettings().GetDRCEpsilon();
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// First build out the board's cache of copper-keepout to copper-zone caches. This is where
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// the bulk of the time is spent, and we can do this in parallel.
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//
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std::vector<ZONE*> antiCopperKeepouts;
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std::vector<ZONE*> copperZones;
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std::vector<std::pair<ZONE*, ZONE*>> toCache;
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std::atomic<size_t> done( 1 );
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int totalCount = 0;
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std::unique_ptr<DRC_RTREE> antiTrackKeepouts = std::make_unique<DRC_RTREE>();
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forEachGeometryItem( { PCB_ZONE_T }, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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ZONE* zone = static_cast<ZONE*>( item );
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if( zone->GetIsRuleArea() && zone->GetDoNotAllowZoneFills() )
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{
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antiCopperKeepouts.push_back( zone );
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}
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else if( zone->GetIsRuleArea() && zone->GetDoNotAllowTracks() )
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{
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for( PCB_LAYER_ID layer : zone->GetLayerSet() )
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antiTrackKeepouts->Insert( zone, layer );
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}
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else if( zone->IsOnCopperLayer() )
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{
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copperZones.push_back( zone );
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}
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totalCount++;
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return true;
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} );
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for( ZONE* ruleArea : antiCopperKeepouts )
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{
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for( ZONE* copperZone : copperZones )
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{
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toCache.push_back( { ruleArea, copperZone } );
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totalCount++;
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}
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}
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auto query_areas =
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[&]( const int idx ) -> size_t
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{
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if( m_drcEngine->IsCancelled() )
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return 0;
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const auto& areaZonePair = toCache[idx];
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ZONE* ruleArea = areaZonePair.first;
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ZONE* copperZone = areaZonePair.second;
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BOX2I areaBBox = ruleArea->GetBoundingBox();
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BOX2I copperBBox = copperZone->GetBoundingBox();
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bool isInside = false;
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if( copperZone->IsFilled() && areaBBox.Intersects( copperBBox ) )
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{
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// Collisions include touching, so we need to deflate outline by enough to
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// exclude it. This is particularly important for detecting copper fills as
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// they will be exactly touching along the entire exclusion border.
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SHAPE_POLY_SET areaPoly = ruleArea->Outline()->CloneDropTriangulation();
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areaPoly.Fracture();
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areaPoly.Deflate( epsilon, CORNER_STRATEGY::ALLOW_ACUTE_CORNERS, ARC_LOW_DEF );
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DRC_RTREE* zoneRTree = board->m_CopperZoneRTreeCache[ copperZone ].get();
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if( zoneRTree )
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{
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for( size_t ii = 0; ii < ruleArea->GetLayerSet().size(); ++ii )
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{
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if( ruleArea->GetLayerSet().test( ii ) )
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{
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PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
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if( zoneRTree->QueryColliding( areaBBox, &areaPoly, layer ) )
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{
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isInside = true;
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break;
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}
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if( m_drcEngine->IsCancelled() )
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return 0;
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}
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}
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}
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}
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if( m_drcEngine->IsCancelled() )
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return 0;
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PTR_PTR_LAYER_CACHE_KEY key = { ruleArea, copperZone, UNDEFINED_LAYER };
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{
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std::unique_lock<std::shared_mutex> writeLock( board->m_CachesMutex );
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board->m_IntersectsAreaCache[ key ] = isInside;
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}
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done.fetch_add( 1 );
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return 1;
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};
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thread_pool& tp = GetKiCadThreadPool();
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auto futures = tp.submit_loop( 0, toCache.size(), query_areas );
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for( auto& ret : futures )
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{
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std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
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while( status != std::future_status::ready )
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{
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reportProgress( done, toCache.size() );
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status = ret.wait_for( std::chrono::milliseconds( 250 ) );
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}
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}
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if( m_drcEngine->IsCancelled() )
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return false;
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// Now go through all the board objects calling the DRC_ENGINE to run the actual disallow
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// tests. These should be reasonably quick using the caches generated above.
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//
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const int progressDelta = 250;
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int ii = static_cast<int>( toCache.size() );
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auto checkTextOnEdgeCuts =
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[&]( BOARD_ITEM* item )
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{
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if( item->Type() == PCB_FIELD_T
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|| item->Type() == PCB_TEXT_T
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|| item->Type() == PCB_TEXTBOX_T
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|| BaseType( item->Type() ) == PCB_DIMENSION_T )
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{
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if( item->GetLayer() == Edge_Cuts )
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{
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std::shared_ptr<DRC_ITEM> drc = DRC_ITEM::Create( DRCE_TEXT_ON_EDGECUTS );
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drc->SetItems( item );
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reportViolation( drc, item->GetPosition(), Edge_Cuts );
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}
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}
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};
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auto checkAntiTrackKeepout =
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[&]( PCB_TRACK* track, ZONE* keepout )
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{
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std::shared_ptr<SHAPE> shape = track->GetEffectiveShape();
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int dummyActual;
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VECTOR2I pos;
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if( keepout->Outline()->Collide( shape.get(), board->m_DRCMaxClearance,
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&dummyActual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
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drcItem->SetItems( track );
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reportViolation( drcItem, pos, track->GetLayerSet().ExtractLayer() );
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}
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};
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auto checkDisallow =
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[&]( BOARD_ITEM* item )
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{
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DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item,
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nullptr, UNDEFINED_LAYER );
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if( constraint.m_DisallowFlags && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
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PCB_LAYER_ID layer = item->GetLayerSet().ExtractLayer();
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wxString msg;
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// Implicit rules reported in checkAntiTrackKeepout
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if( constraint.GetParentRule()->m_Implicit )
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return;
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msg.Printf( drcItem->GetErrorText() + wxS( " (%s)" ), constraint.GetName() );
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drcItem->SetErrorMessage( msg );
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drcItem->SetItems( item );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, item->GetPosition(), layer );
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}
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};
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forEachGeometryItem( {}, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_ON_EDGECUTS ) )
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checkTextOnEdgeCuts( item );
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_ALLOWED_ITEMS ) )
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{
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if( ZONE* zone = dynamic_cast<ZONE*>( item ) )
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{
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if( zone->GetIsRuleArea() && zone->HasKeepoutParametersSet() )
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return true;
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}
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item->ClearFlags( HOLE_PROXY ); // Just in case
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if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
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{
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PCB_TRACK* track = static_cast<PCB_TRACK*>( item );
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PCB_LAYER_ID layer = track->GetLayer();
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antiTrackKeepouts->QueryColliding( track, layer, layer,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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return true;
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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checkAntiTrackKeepout( track, static_cast<ZONE*>( other ) );
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return !m_drcEngine->IsCancelled();
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},
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board->m_DRCMaxPhysicalClearance );
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}
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checkDisallow( item );
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if( item->HasHole() )
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{
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item->SetFlags( HOLE_PROXY );
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checkDisallow( item );
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item->ClearFlags( HOLE_PROXY );
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}
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}
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if( !reportProgress( ii++, totalCount, progressDelta ) )
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return false;
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return true;
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} );
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_DISALLOW> dummy;
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}
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