mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-15 10:43:15 +02:00
bbc25cd694
Also move courtyard testing flags to BoardSettings API. Both are still stored in the config until we decide where they go in order to prevent prematurely disturbing the board file format. Fixes: lp:684067 * https://bugs.launchpad.net/kicad/+bug/684067 (cherry picked from commit 5399f60)
463 lines
16 KiB
C++
463 lines
16 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @file board_design_settings.cpp
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* BOARD_DESIGN_SETTINGS class functions.
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*/
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#include <fctsys.h>
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#include <common.h>
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#include <layers_id_colors_and_visibility.h>
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#include <pcbnew.h>
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#include <board_design_settings.h>
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#include <class_track.h>
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#include <convert_to_biu.h>
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#include <kiface_i.h>
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#define TestMissingCourtyardKey wxT( "TestMissingCourtyard" )
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#define TestFootprintCourtyardKey wxT( "TestFootprintCourtyard" )
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#define MinHoleSeparationKey wxT( "MinHoleSeparation" )
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BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS() :
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m_Pad_Master( NULL )
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{
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LSET all_set = LSET().set();
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m_enabledLayers = all_set; // All layers enabled at first.
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// SetCopperLayerCount() will adjust this.
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SetVisibleLayers( all_set );
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// set all but hidden text as visible.
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m_visibleElements = ~( 1 << GAL_LAYER_INDEX( LAYER_MOD_TEXT_INVISIBLE ) );
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SetCopperLayerCount( 2 ); // Default design is a double sided board
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// via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA).
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m_CurrentViaType = VIA_THROUGH;
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// if true, when creating a new track starting on an existing track, use this track width
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m_UseConnectedTrackWidth = false;
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m_BlindBuriedViaAllowed = false; // true to allow blind/buried vias
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m_MicroViasAllowed = false; // true to allow micro vias
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m_DrawSegmentWidth = Millimeter2iu( DEFAULT_GRAPHIC_THICKNESS ); // current graphic line width (not EDGE layer)
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m_EdgeSegmentWidth = Millimeter2iu( DEFAULT_PCB_EDGE_THICKNESS ); // current graphic line width (EDGE layer only)
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m_PcbTextWidth = Millimeter2iu( DEFAULT_TEXT_PCB_THICKNESS ); // current Pcb (not module) Text width
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m_PcbTextSize = wxSize( Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ),
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Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ) ); // current Pcb (not module) Text size
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m_useCustomTrackVia = false;
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m_customTrackWidth = Millimeter2iu( DEFAULT_CUSTOMTRACKWIDTH );
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m_customViaSize.m_Diameter = Millimeter2iu( DEFAULT_VIASMINSIZE );
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m_customViaSize.m_Drill = Millimeter2iu( DEFAULT_VIASMINDRILL );
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m_TrackMinWidth = Millimeter2iu( DEFAULT_TRACKMINWIDTH ); // track min width
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m_ViasMinSize = Millimeter2iu( DEFAULT_VIASMINSIZE ); // via (not uvia) min diam
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m_ViasMinDrill = Millimeter2iu( DEFAULT_VIASMINDRILL ); // via (not uvia) min drill diam
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m_MicroViasMinSize = Millimeter2iu( DEFAULT_MICROVIASMINSIZE );// uvia (not via) min diam
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m_MicroViasMinDrill = Millimeter2iu( DEFAULT_MICROVIASMINDRILL );// uvia (not via) min drill diam
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// Global mask margins:
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m_SolderMaskMargin = Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ); // Solder mask margin
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m_SolderMaskMinWidth = Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ); // Solder mask min width
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m_SolderPasteMargin = 0; // Solder paste margin absolute value
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m_SolderPasteMarginRatio = 0.0; // Solder pask margin ratio value of pad size
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// The final margin is the sum of these 2 values
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// Usually < 0 because the mask is smaller than pad
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// Layer thickness for 3D viewer
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m_boardThickness = Millimeter2iu( DEFAULT_BOARD_THICKNESS_MM );
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m_viaSizeIndex = 0;
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m_trackWidthIndex = 0;
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// Default values for the footprint editor and fp creation
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// (also covers footprints created on the fly by micor-waves tools)
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m_ModuleTextSize = wxSize( Millimeter2iu( DEFAULT_TEXT_MODULE_SIZE ),
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Millimeter2iu( DEFAULT_TEXT_MODULE_SIZE ) );
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m_ModuleTextWidth = Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS );
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m_ModuleSegmentWidth = Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS );
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// These values will be overriden by config values after reading the config
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// Default ref text on fp creation. if empty, use footprint name as default
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m_RefDefaultText = wxT( "REF**" );
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m_RefDefaultVisibility = true; // Default ref text visibility on fp creation
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m_RefDefaultlayer = int( F_SilkS ); // Default ref text layer on fp creation
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// Default value text on fp creation. if empty, use footprint name as default
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m_ValueDefaultText = wxEmptyString;
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m_ValueDefaultVisibility = true;
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m_ValueDefaultlayer = int( F_Fab );
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}
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// Add parameters to save in project config.
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// values are saved in mm
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void BOARD_DESIGN_SETTINGS::AppendConfigs( PARAM_CFG_ARRAY* aResult )
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{
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m_Pad_Master.AppendConfigs( aResult );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeV" ),
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&m_PcbTextSize.y,
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Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeH" ),
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&m_PcbTextSize.x,
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Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ), TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextThickness" ),
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&m_PcbTextWidth,
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Millimeter2iu(DEFAULT_TEXT_PCB_THICKNESS ),
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeV" ),
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&m_ModuleTextSize.y,
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DEFAULT_TEXT_MODULE_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeH" ),
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&m_ModuleTextSize.x,
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DEFAULT_TEXT_MODULE_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeThickness" ),
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&m_ModuleTextWidth,
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Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS ), 1, TEXTS_MAX_WIDTH,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskClearance" ),
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&m_SolderMaskMargin,
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Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ), 0, Millimeter2iu( 1.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskMinWidth" ),
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&m_SolderMaskMinWidth,
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Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ), 0, Millimeter2iu( 0.5 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "DrawSegmentWidth" ),
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&m_DrawSegmentWidth,
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Millimeter2iu( DEFAULT_GRAPHIC_THICKNESS ),
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "BoardOutlineThickness" ),
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&m_EdgeSegmentWidth,
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Millimeter2iu( DEFAULT_PCB_EDGE_THICKNESS ),
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleOutlineThickness" ),
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&m_ModuleSegmentWidth,
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Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS ),
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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}
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bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName )
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{
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NETCLASSPTR netClass = m_NetClasses.Find( aNetClassName );
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bool lists_sizes_modified = false;
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// if not found (should not happen) use the default
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if( netClass == NULL )
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netClass = m_NetClasses.GetDefault();
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m_currentNetClassName = netClass->GetName();
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// Initialize others values:
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if( m_ViasDimensionsList.size() == 0 )
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{
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VIA_DIMENSION viadim;
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lists_sizes_modified = true;
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m_ViasDimensionsList.push_back( viadim );
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}
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if( m_TrackWidthList.size() == 0 )
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{
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lists_sizes_modified = true;
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m_TrackWidthList.push_back( 0 );
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}
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/* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
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* are always the Netclass values
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*/
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if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
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{
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lists_sizes_modified = true;
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m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
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}
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if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
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{
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lists_sizes_modified = true;
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m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
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}
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if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
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{
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lists_sizes_modified = true;
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m_TrackWidthList[0] = netClass->GetTrackWidth();
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}
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if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
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SetViaSizeIndex( m_ViasDimensionsList.size() );
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if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
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SetTrackWidthIndex( m_TrackWidthList.size() );
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return lists_sizes_modified;
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}
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int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue()
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{
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int clearance = m_NetClasses.GetDefault()->GetClearance();
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//Read list of Net Classes
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for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
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{
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NETCLASSPTR netclass = nc->second;
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clearance = std::max( clearance, netclass->GetClearance() );
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}
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return clearance;
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}
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int BOARD_DESIGN_SETTINGS::GetSmallestClearanceValue()
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{
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int clearance = m_NetClasses.GetDefault()->GetClearance();
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//Read list of Net Classes
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for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
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{
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NETCLASSPTR netclass = nc->second;
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clearance = std::min( clearance, netclass->GetClearance() );
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}
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return clearance;
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}
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int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaSize()
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{
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NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
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return netclass->GetuViaDiameter();
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}
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int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaDrill()
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{
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NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
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return netclass->GetuViaDrill();
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}
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void BOARD_DESIGN_SETTINGS::SetViaSizeIndex( unsigned aIndex )
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{
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if( aIndex >= m_ViasDimensionsList.size() )
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m_viaSizeIndex = m_ViasDimensionsList.size();
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else
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m_viaSizeIndex = aIndex;
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m_useCustomTrackVia = false;
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}
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int BOARD_DESIGN_SETTINGS::GetCurrentViaDrill() const
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{
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int drill;
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if( m_useCustomTrackVia )
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drill = m_customViaSize.m_Drill;
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else
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drill = m_ViasDimensionsList[m_viaSizeIndex].m_Drill;
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return drill > 0 ? drill : -1;
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}
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void BOARD_DESIGN_SETTINGS::SetTrackWidthIndex( unsigned aIndex )
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{
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if( aIndex >= m_TrackWidthList.size() )
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m_trackWidthIndex = m_TrackWidthList.size();
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else
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m_trackWidthIndex = aIndex;
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m_useCustomTrackVia = false;
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}
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int BOARD_DESIGN_SETTINGS::GetMinHoleSeparation() const
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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int value;
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config->Read( MinHoleSeparationKey, &value, Millimeter2iu( DEFAULT_HOLETOHOLEMIN ) );
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return value;
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}
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void BOARD_DESIGN_SETTINGS::SetMinHoleSeparation( int aDistance )
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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config->Write( MinHoleSeparationKey, aDistance );
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}
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bool BOARD_DESIGN_SETTINGS::RequireCourtyardDefinitions() const
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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bool value;
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config->Read( TestMissingCourtyardKey, &value, false );
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return value;
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}
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void BOARD_DESIGN_SETTINGS::SetRequireCourtyardDefinitions( bool aRequire )
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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config->Write( TestMissingCourtyardKey, aRequire );
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}
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bool BOARD_DESIGN_SETTINGS::ProhibitOverlappingCourtyards() const
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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bool value;
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config->Read( TestFootprintCourtyardKey, &value, false );
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return value;
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}
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void BOARD_DESIGN_SETTINGS::SetProhibitOverlappingCourtyards( bool aRequire )
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{
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// 6.0 TODO: we need to decide where these go, but until then don't disturb the
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// file format unnecessarily.
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wxConfigBase* config = Kiface().KifaceSettings();
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config->Write( TestFootprintCourtyardKey, aRequire );
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}
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void BOARD_DESIGN_SETTINGS::SetVisibleAlls()
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{
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SetVisibleLayers( LSET().set() );
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m_visibleElements = -1;
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}
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void BOARD_DESIGN_SETTINGS::SetLayerVisibility( PCB_LAYER_ID aLayer, bool aNewState )
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{
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if( aNewState && IsLayerEnabled( aLayer ) )
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m_visibleLayers.set( aLayer, true );
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else
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m_visibleLayers.set( aLayer, false );
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}
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void BOARD_DESIGN_SETTINGS::SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState )
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{
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if( aNewState )
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m_visibleElements |= 1 << GAL_LAYER_INDEX( aElementCategory );
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else
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m_visibleElements &= ~( 1 << GAL_LAYER_INDEX( aElementCategory ) );
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}
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void BOARD_DESIGN_SETTINGS::SetCopperLayerCount( int aNewLayerCount )
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{
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// if( aNewLayerCount < 2 ) aNewLayerCount = 2;
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m_copperLayerCount = aNewLayerCount;
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// ensure consistency with the m_EnabledLayers member
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#if 0
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// was:
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m_enabledLayers &= ~ALL_CU_LAYERS;
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m_enabledLayers |= LAYER_BACK;
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if( m_copperLayerCount > 1 )
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m_enabledLayers |= LAYER_FRONT;
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for( LAYER_NUM ii = LAYER_N_2; ii < aNewLayerCount - 1; ++ii )
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m_enabledLayers |= GetLayerSet( ii );
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#else
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// Update only enabled copper layers mask
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m_enabledLayers &= ~LSET::AllCuMask();
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m_enabledLayers |= LSET::AllCuMask( aNewLayerCount );
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#endif
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}
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void BOARD_DESIGN_SETTINGS::SetEnabledLayers( LSET aMask )
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{
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// Back and front layers are always enabled.
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aMask.set( B_Cu ).set( F_Cu );
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m_enabledLayers = aMask;
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// A disabled layer cannot be visible
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m_visibleLayers &= aMask;
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// update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
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m_copperLayerCount = ( aMask & LSET::AllCuMask() ).count();
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}
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#ifndef NDEBUG
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struct list_size_check {
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list_size_check()
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{
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// Int (the type used for saving visibility settings) is only 32 bits guaranteed,
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// be sure that we do not cross the limit
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assert( GAL_LAYER_INDEX( GAL_LAYER_ID_BITMASK_END ) <= 32 );
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};
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};
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static list_size_check check;
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#endif
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