kicad-source/pcbnew/dialogs/panel_setup_rules_help_9more_examples.h

// Do not edit this file, it is autogenerated by CMake from the .md file
_HKI( "### More Examples\n"
"\n"
"    (rule \"copper keepout\"\n"
"       (constraint disallow track via zone)\n"
"       (condition \"A.intersectsArea('zone3')\"))\n"
"\n"
"\n"
"    (rule \"BGA neckdown\"\n"
"       (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
"       (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
"       (condition \"A.intersectsCourtyard('U3')\"))\n"
"\n"
"\n"
"    # prevent silk over tented vias\n"
"    (rule silk_over_via\n"
"       (constraint silk_clearance (min 0.2mm))\n"
"       (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
"\n"
"\n"
"    (rule \"Distance between Vias of Different Nets\"\n"
"        (constraint hole_to_hole (min 0.254mm))\n"
"        (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))\n"
"\n"
"    (rule \"Clearance between Pads of Different Nets\"\n"
"        (constraint clearance (min 3.0mm))\n"
"        (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))\n"
"\n"
"\n"
"    (rule \"Via Hole to Track Clearance\"\n"
"        (constraint hole_clearance (min 0.254mm))\n"
"        (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
"\n"
"    (rule \"Pad to Track Clearance\"\n"
"        (constraint clearance (min 0.2mm))\n"
"        (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n"
"\n"
"\n"
"    (rule \"clearance-to-1mm-cutout\"\n"
"        (constraint edge_clearance (min 0.8mm))\n"
"        (condition \"A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm\"))\n"
"\n"
"\n"
"    (rule \"Max Drill Hole Size Mechanical\"\n"
"        (constraint hole_size (max 6.3mm))\n"
"        (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
"\n"
"    (rule \"Max Drill Hole Size PTH\"\n"
"        (constraint hole_size (max 6.35mm))\n"
"        (condition \"A.Pad_Type == 'Through-hole'\"))\n"
"\n"
"\n"
"    # Specify an optimal gap for a particular diff-pair\n"
"    (rule \"dp clock gap\"\n"
"        (constraint diff_pair_gap (opt \"0.8mm\"))\n"
"        (condition \"A.inDiffPair('/CLK')\"))\n"
"\n"
"    # Specify a larger clearance around any diff-pair\n"
"    (rule \"dp clearance\"\n"
"        (constraint clearance (min \"1.5mm\"))\n"
"        (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
"\n"
"\n"
"    # Don't use thermal reliefs on heatsink pads\n"
"    (rule heat_sink_pad\n"
"        (constraint zone_connection solid)\n"
"        (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
"\n"
"    # Require all four thermal relief spokes to connect to parent zone\n"
"    (rule fully_spoked_pads\n"
"        (constraint min_resolved_spokes 4))\n"
"\n"
"    # Set thermal relief gap & spoke width for all zones\n"
"    (rule defined_relief\n"
"        (constraint thermal_relief_gap (min 10mil))\n"
"        (constraint thermal_spoke_width (min 12mil)))\n"
"\n"
"    # Override thermal relief gap & spoke width for GND and PWR zones\n"
"    (rule defined_relief_pwr\n"
"        (constraint thermal_relief_gap (min 10mil))\n"
"        (constraint thermal_spoke_width (min 12mil))\n"
"        (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n"
"\n"
"    # Prevent copper fills under the courtyards of capacitors\n"
"    (rule no_copper_under_caps\n"
"        (constraint physical_clearance (min 0mm))\n"
"        (condition \"A.Type == 'Zone' && B.Reference == 'C*'\"))\n"
"\n"
"\n"
"    # Prevent solder wicking from SMD pads\n"
"    (rule holes_in_pads\n"
"        (constraint physical_hole_clearance (min 0.2mm))\n"
"        (condition \"B.Pad_Type == 'SMD'\"))\n"
"\n"
"    # Disallow solder mask margin overrides\n"
"    (rule \"disallow solder mask margin overrides\"\n"
"        (constraint assertion \"A.Soldermask_Margin_Override == null\")\n"
"        (condition \"A.Type == 'Pad'\"))\n"
"\n"
"\n"
"    # Enforce a mechanical clearance between components and board edge\n"
"    (rule front_mechanical_board_edge_clearance\n"
"        (layer \"F.Courtyard\")\n"
"        (constraint physical_clearance (min 3mm))\n"
"        (condition \"B.Layer == 'Edge.Cuts'\"))\n"
"\n"
"\n"
"    # Allow silk intersection with board edge for connectors\n"
"    (rule silk_board_edge_clearance\n"
"        (constraint silk_clearance)\n"
"        (severity ignore)\n"
"        (condition \"A.memberOfFootprint('J*') && B.Layer=='Edge.Cuts'\"))\n"
"\n"
"\n"
"    # Check current-carrying capacity\n"
"    (rule high-current\n"
"        (constraint track_width (min 1.0mm))\n"
"        (constraint connection_width (min 0.8mm))\n"
"        (condition \"A.hasNetclass('Power')\"))\n"
"\n"
"\n"
"    # Separate drill bit and milling cutter size constraints\n"
"    (rule \"Plated through-hole size\"\n"
"        (constraint hole_size (min 0.2mm) (max 6.35mm))\n"
"        (condition \"A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y\"))\n"
"    (rule \"Plated slot size\"\n"
"        (constraint hole_size (min 0.5mm))\n"
"        (condition \"A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y\"))\n"
"\n"
"\n"
"    # Allow blind/buried to micro-via hole-to-hole violations when it is known that\n"
"    # the fab will mechanically drill blind/buried via holes -before- laser drilling \n"
"    # micro-vias.\n"
"    (rule hole_to_hole_uvia_exclusion\n"
"        (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'\")\n"
"        (constraint hole_to_hole)\n"
"        (severity ignore))\n"
"\n"
"\n"
"    # No solder mask expansion for vias.\n"
"    (rule \"no mask expansion on vias\"\n"
"        (constraint solder_mask_expansion (opt 0mm))\n"
"        (condition \"A.type == via\"))\n"
"\n"
"\n"
"    # Remove solder paste from DNP footprints.\n"
"    (rule remove_solder_paste_from_DNP\n"
"        (constraint solder_paste_abs_margin (opt -50mm))\n"
"        (condition \"A.Do_not_Populate\"))\n"
"\n"
"" );