mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-14 02:03:12 +02:00
46df421064
Each pad group is allowed to short nets with other pads in its group. Legacy footprints with the "net tie" keyword hack will get a single group auto-created with all the footprint's pads in it. DRC and the router now allow a track to collide with copper graphic items while entering a net-tie pad as long as the closest point in the collision is within the pad. DRC (and the footprint checker) now check for copper items in the footprint shorting pads which are not in the same pad group. Fixes https://gitlab.com/kicad/code/kicad/issues/2265
341 lines
4.5 KiB
Plaintext
341 lines
4.5 KiB
Plaintext
#
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# This program source code file is part of KiCad, a free EDA CAD application.
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#
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# Copyright (C) 2012 CERN.
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# Copyright (C) 2019-2022 KiCad Developers, see AUTHORS.txt for contributors.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, you may find one here:
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# http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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# or you may search the http://www.gnu.org website for the version 2 license,
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# or you may write to the Free Software Foundation, Inc.,
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# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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#
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# These are the keywords for the Pcbnew s-expression file format.
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add_net
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addsublayer
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aligned
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allowed
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allow_missing_courtyard
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allow_soldermask_bridges
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allow_soldermask_bridges_in_footprints
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anchor
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angle
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arc
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arc_segments
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area
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arrow1a
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arrow1b
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arrow2a
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arrow2b
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arrow_length
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at
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attr
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autoplace_cost90
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autoplace_cost180
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aux_axis_origin
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bevelled
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blind
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blind_buried_vias_allowed
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board_only
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bold
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bottom
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bottom_left
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bottom_right
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castellated_pads
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center
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chamfer
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chamfer_ratio
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circle
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clearance
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clearance_min
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color
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comment
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company
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connect
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connect_pads
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copperpour
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copper_finish
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crossbar
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custom
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outline
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convexhull
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copper_line_width
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copper_text_dims
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courtyard_line_width
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data
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date
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defaults
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descr
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die_length
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dielectric_constraints
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dimension
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diff_pair_width
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diff_pair_gap
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dimension_precision
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dimension_units
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drawings
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drill
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edge
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edge_clearance
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edge_cuts_line_width
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edge_connector
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edge_plating
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edge_width
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effects
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end
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epsilon_r
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exclude_from_pos_files
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exclude_from_bom
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extension_height
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extension_offset
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fab_layers_line_width
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fab_layers_text_dims
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face
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feature1
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feature2
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fill
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fill_segments
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filled_polygon
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filled_areas_thickness
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fillet
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font
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format
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footprint
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footprints
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fp_arc
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fp_circle
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fp_curve
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fp_line
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fp_poly
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fp_rect
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fp_text
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fp_text_box
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free
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full
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general
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generator
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grid_origin
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group
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gr_arc
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gr_circle
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gr_curve
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gr_line
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gr_poly
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gr_rect
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gr_text
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gr_text_box
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hatch
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hatch_thickness
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hatch_gap
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hatch_orientation
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hatch_smoothing_level
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hatch_smoothing_value
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hatch_border_algorithm
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hatch_min_hole_area
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height
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hide
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hole_to_hole_min
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host
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id
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image
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island
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island_removal_mode
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island_area_min
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italic
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justify
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keepout
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keep_end_layers
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keep_text_aligned
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keep_upright
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kicad_pcb
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knockout
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last_trace_width
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layer
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layers
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leader
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leader_length
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left
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linear
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line_spacing
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links
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locked
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loss_tangent
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max_error
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material
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members
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micro
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mid
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min_thickness
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mirror
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mod_edge_width
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mod_text_size
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mod_text_width
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mode
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model
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module
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name
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net
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net_class
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net_name
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net_tie_pad_groups
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nets
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no
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no_connects
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none
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not_allowed
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np_thru_hole
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offset
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opacity
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options
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orientation
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orthogonal
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other_layers_line_width
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other_layers_text_dims
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oval
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override_value
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pad
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pads
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pad_drill
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pad_size
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pad_to_mask_clearance
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pad_to_paste_clearance
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pad_to_paste_clearance_ratio
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pad_prop_bga
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pad_prop_fiducial_loc
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pad_prop_fiducial_glob
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pad_prop_castellated
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pad_prop_testpoint
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pad_prop_heatsink
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padvia
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private_layers
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property
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page
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paper
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path
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pcb_text_size
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pcb_text_width
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pcbplotparams
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pinfunction
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pintype
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placed
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plus
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polygon
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portrait
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precision
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prefix
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primitives
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priority
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pts
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radial
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radius
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rev
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rect
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rect_delta
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reference
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remove_unused_layers
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render_cache
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right
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rotate
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roundrect
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roundrect_rratio
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scale
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segment
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segment_width
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setup
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silk_line_width
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silk_text_dims
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size
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smd
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smoothing
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solder_mask_margin
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solder_mask_min_width
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solder_paste_margin
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solder_paste_margin_ratio
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solder_paste_ratio
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solid
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stackup
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start
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status
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stroke
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style
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suffix
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suppress_zeroes
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tags
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target
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title
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title_block
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teardrop
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tedit
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text_frame
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text_position_mode
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thermal_width
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thermal_gap
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thermal_bridge_angle
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thermal_bridge_width
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thickness
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through_hole
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through_hole_min
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top
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top_left
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top_right
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trace_width
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tracks
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track_end
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trace_min
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trace_clearance
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trapezoid
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thru
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thru_hole
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thru_hole_only
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tstamp
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type
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units
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units_format
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unlocked
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user
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user_diff_pair
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user_trace_width
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user_via
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uvia_dia
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uvia_drill
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uvia_min_drill
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uvia_min_size
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uvia_size
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uvias_allowed
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value
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version
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via
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vias
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via_dia
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via_drill
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via_min_annulus
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via_min_drill
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via_min_size
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via_size
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virtual
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visible_elements
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width
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x
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xy
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xyz
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yes
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zone
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zone_45_only
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zone_clearance
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zone_connect
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zone_type
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zones
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