mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-15 10:43:15 +02:00
3d6d8b9946
Like the DSNLEXER header, this has visibility in over 700 files, whereas well under half actually use any of it (quite a bit, but not all, of it actually via DSNLEXER) Many places already forward-declare the OUTPUTFORMATTER type, by doing that for the others, it still possible to use the non-IO methods without having to see richio.h.
671 lines
19 KiB
C++
671 lines
19 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019 CERN
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* Copyright (C) 2022-2023 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <kiface_base.h>
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#include <macros.h>
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#include <pcb_edit_frame.h>
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#include <board.h>
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#include <board_design_settings.h>
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#include <board_item.h>
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#include <footprint.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <zone.h>
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#include <cstdio>
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#include <vector>
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#include <ki_exception.h>
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#include <locale_io.h>
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#include <reporter.h>
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#include <richio.h>
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#include <exporters/board_exporter_base.h>
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#include <wx/log.h>
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static double iu2hyp( double iu )
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{
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return iu / 1e9 / 0.0254;
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}
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class HYPERLYNX_EXPORTER;
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class HYPERLYNX_PAD_STACK
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{
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public:
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friend class HYPERLYNX_EXPORTER;
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HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad );
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HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia );
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~HYPERLYNX_PAD_STACK(){};
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bool IsThrough() const
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{
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return m_type == PAD_ATTRIB::NPTH || m_type == PAD_ATTRIB::PTH;
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}
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bool operator==( const HYPERLYNX_PAD_STACK& other ) const
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{
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if( m_shape != other.m_shape )
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return false;
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if( m_type != other.m_type )
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return false;
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if( IsThrough() && other.IsThrough() && m_drill != other.m_drill )
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return false;
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if( m_sx != other.m_sx )
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return false;
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if( m_sy != other.m_sy )
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return false;
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if( m_layers != other.m_layers )
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return false;
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if( m_angle != other.m_angle )
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return false;
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return true;
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}
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void SetId( int id )
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{
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m_id = id;
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}
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int GetId() const
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{
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return m_id;
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}
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bool IsEmpty() const
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{
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LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers();
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LSET outLayers = m_layers & layerMask;
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return outLayers.none();
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}
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private:
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BOARD* m_board;
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int m_id;
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int m_drill;
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PAD_SHAPE m_shape;
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int m_sx, m_sy;
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double m_angle;
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LSET m_layers;
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PAD_ATTRIB m_type;
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};
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class HYPERLYNX_EXPORTER : public BOARD_EXPORTER_BASE
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{
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public:
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HYPERLYNX_EXPORTER() : m_polyId( 1 )
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{
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}
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~HYPERLYNX_EXPORTER(){};
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virtual bool Run() override;
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private:
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HYPERLYNX_PAD_STACK* addPadStack( HYPERLYNX_PAD_STACK stack )
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{
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for( HYPERLYNX_PAD_STACK* p : m_padStacks )
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{
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if( *p == stack )
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return p;
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}
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stack.SetId( m_padStacks.size() );
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m_padStacks.push_back( new HYPERLYNX_PAD_STACK( stack ) );
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return m_padStacks.back();
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}
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const std::string formatPadShape( const HYPERLYNX_PAD_STACK& aStack )
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{
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int shapeId = 0;
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char buf[1024];
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switch( aStack.m_shape )
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{
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case PAD_SHAPE::CIRCLE:
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case PAD_SHAPE::OVAL:
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shapeId = 0;
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break;
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case PAD_SHAPE::ROUNDRECT:
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shapeId = 2;
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break;
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case PAD_SHAPE::RECTANGLE:
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shapeId = 1;
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break;
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default:
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if( m_reporter )
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{
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m_reporter->Report( _( "File contains pad shapes that are not supported by the "
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"Hyperlynx exporter (supported shapes are oval, rectangle, "
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"rounded rectangle, and circle)." ),
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RPT_SEVERITY_WARNING );
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m_reporter->Report( _( "They have been exported as oval pads." ),
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RPT_SEVERITY_INFO );
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}
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shapeId = 0;
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break;
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}
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snprintf( buf, sizeof( buf ), "%d, %.9f, %.9f, %.1f, M",
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shapeId,
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iu2hyp( aStack.m_sx ),
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iu2hyp( aStack.m_sy ),
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aStack.m_angle );
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return buf;
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}
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bool generateHeaders();
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bool writeBoardInfo();
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bool writeStackupInfo();
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bool writeDevices();
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bool writePadStacks();
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bool writeNets();
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bool writeNetObjects( const std::vector<BOARD_ITEM*>& aObjects );
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void writeSinglePadStack( HYPERLYNX_PAD_STACK& aStack );
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const std::vector<BOARD_ITEM*> collectNetObjects( int netcode );
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private:
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std::vector<HYPERLYNX_PAD_STACK*> m_padStacks;
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std::map<BOARD_ITEM*, HYPERLYNX_PAD_STACK*> m_padMap;
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std::shared_ptr<FILE_OUTPUTFORMATTER> m_out;
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int m_polyId;
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};
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HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad )
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{
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// TODO(JE) padstacks
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m_board = aBoard;
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m_sx = aPad->GetSize( PADSTACK::ALL_LAYERS ).x;
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m_sy = aPad->GetSize( PADSTACK::ALL_LAYERS ).y;
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m_angle = 180.0 - aPad->GetOrientation().AsDegrees();
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if( m_angle < 0.0 )
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m_angle += 360.0;
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m_layers = aPad->GetLayerSet();
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m_drill = aPad->GetDrillSize().x;
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m_shape = aPad->GetShape( PADSTACK::ALL_LAYERS );
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m_type = PAD_ATTRIB::PTH;
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m_id = 0;
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}
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HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia )
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{
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m_board = aBoard;
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m_sx = aVia->GetWidth();
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m_sy = aVia->GetWidth();
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m_angle = 0;
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m_layers = aVia->GetLayerSet();
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m_drill = aVia->GetDrillValue();
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m_shape = PAD_SHAPE::CIRCLE;
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m_type = PAD_ATTRIB::PTH;
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m_id = 0;
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}
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bool HYPERLYNX_EXPORTER::generateHeaders()
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{
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m_out->Print( 0, "{VERSION=2.14}\n" );
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m_out->Print( 0, "{UNITS=ENGLISH LENGTH}\n\n" );
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return true;
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}
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void HYPERLYNX_EXPORTER::writeSinglePadStack( HYPERLYNX_PAD_STACK& aStack )
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{
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LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers();
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LSET outLayers = aStack.m_layers & layerMask;
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if( outLayers.none() )
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return;
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m_out->Print( 0, "{PADSTACK=%d, %.9f\n", aStack.m_id, iu2hyp( aStack.m_drill ) );
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if( outLayers == layerMask )
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{
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m_out->Print( 1, "(\"MDEF\", %s)\n", formatPadShape( aStack ).c_str() );
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}
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else
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{
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for( PCB_LAYER_ID l : outLayers.Seq() )
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{
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m_out->Print( 1, "(\"%s\", %s)\n",
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(const char*) m_board->GetLayerName( l ).c_str(),
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formatPadShape( aStack ).c_str() );
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}
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}
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m_out->Print( 0, "}\n\n" );
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}
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bool HYPERLYNX_EXPORTER::writeBoardInfo()
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{
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SHAPE_POLY_SET outlines;
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m_out->Print( 0, "{BOARD \"%s\"\n", (const char*) m_board->GetFileName().c_str() );
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if( !m_board->GetBoardPolygonOutlines( outlines ) )
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{
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wxLogError( _( "Board outline is malformed. Run DRC for a full analysis." ) );
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return false;
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}
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for( int o = 0; o < outlines.OutlineCount(); o++ )
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{
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const SHAPE_LINE_CHAIN& outl = outlines.COutline( o );
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for( int i = 0; i < outl.SegmentCount(); i++ )
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{
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const SEG& s = outl.CSegment( i );
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m_out->Print( 1, "(PERIMETER_SEGMENT X1=%.9f Y1=%.9f X2=%.9f Y2=%.9f)\n",
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iu2hyp( s.A.x ),
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iu2hyp( s.A.y ),
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iu2hyp( s.B.x ),
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iu2hyp( s.B.y ) );
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}
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}
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m_out->Print( 0, "}\n\n" );
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return true;
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}
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bool HYPERLYNX_EXPORTER::writeStackupInfo()
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{
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/* Format:
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* {STACKUP
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* (SIGNAL T=thickness [P=plating_thickness] [C=constant] L=layer_name [M=material_name]) [comment]
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* (DIELECTRIC T=thickness [C=constant] [L=layer_name] [M=material_name]) [comment]
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* }
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* name length is <= 20 chars
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*/
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LSEQ layers = m_board->GetDesignSettings().GetEnabledLayers().CuStack();
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// Get the board physical stackup structure
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const BOARD_STACKUP& stackup = m_board->GetDesignSettings().GetStackupDescriptor();
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m_out->Print( 0, "{STACKUP\n" );
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wxString layer_name; // The last copper layer name used in stackup
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for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
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{
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if( item->GetType() == BS_ITEM_TYPE_COPPER )
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{
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layer_name = m_board->GetLayerName( item->GetBrdLayerId() );
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int plating_thickness = 0;
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double resistivity = 1.724e-8; // Good for copper
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m_out->Print( 1, "(SIGNAL T=%g P=%g C=%g L=\"%.20s\" M=COPPER)\n",
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iu2hyp( item->GetThickness( 0 ) ),
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iu2hyp( plating_thickness ),
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resistivity,
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TO_UTF8( layer_name ) );
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}
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else if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC )
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{
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if( item->GetSublayersCount() < 2 )
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{
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m_out->Print( 1, "(DIELECTRIC T=%g C=%g L=\"DE_%.17s\" M=\"%.20s\")\n",
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iu2hyp( item->GetThickness( 0 ) ),
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item->GetEpsilonR( 0 ),
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TO_UTF8( layer_name ),
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TO_UTF8( item->GetMaterial( 0 ) ) );
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}
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else for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
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{
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m_out->Print( 1, "(DIELECTRIC T=%g C=%g L=\"DE%d_%.16s\" M=\"%.20s\")\n",
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iu2hyp( item->GetThickness( idx ) ),
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item->GetEpsilonR( idx ),
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idx,
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TO_UTF8( layer_name ),
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TO_UTF8( item->GetMaterial( idx ) ) );
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}
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}
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}
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m_out->Print( 0, "}\n\n" );
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return true;
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}
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bool HYPERLYNX_EXPORTER::writeDevices()
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{
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m_out->Print( 0, "{DEVICES\n" );
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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wxString ref = footprint->GetReference();
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wxString layerName = m_board->GetLayerName( footprint->GetLayer() );
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if( ref.IsEmpty() )
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ref = wxT( "EMPTY" );
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m_out->Print( 1, "(? REF=\"%s\" L=\"%s\")\n",
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(const char*) ref.c_str(),
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(const char*) layerName.c_str() );
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}
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m_out->Print( 0, "}\n\n" );
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return true;
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}
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bool HYPERLYNX_EXPORTER::writePadStacks()
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{
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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HYPERLYNX_PAD_STACK* ps = addPadStack( HYPERLYNX_PAD_STACK( m_board, pad ) );
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m_padMap[pad] = ps;
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}
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}
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for( PCB_TRACK* track : m_board->Tracks() )
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{
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if( PCB_VIA* via = dyn_cast<PCB_VIA*>( track ) )
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{
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HYPERLYNX_PAD_STACK* ps = addPadStack( HYPERLYNX_PAD_STACK( m_board, via ) );
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m_padMap[via] = ps;
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}
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}
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for( HYPERLYNX_PAD_STACK* pstack : m_padStacks )
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writeSinglePadStack( *pstack );
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return true;
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}
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bool HYPERLYNX_EXPORTER::writeNetObjects( const std::vector<BOARD_ITEM*>& aObjects )
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{
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for( BOARD_ITEM* item : aObjects )
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{
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if( PAD* pad = dyn_cast<PAD*>( item ) )
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{
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auto pstackIter = m_padMap.find( pad );
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if( pstackIter != m_padMap.end() )
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{
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wxString ref = pad->GetParentFootprint()->GetReference();
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if( ref.IsEmpty() )
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ref = wxT( "EMPTY" );
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wxString padName = pad->GetNumber();
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if( padName.IsEmpty() )
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padName = wxT( "1" );
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m_out->Print( 1, "(PIN X=%.10f Y=%.10f R=\"%s.%s\" P=%d)\n",
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iu2hyp( pad->GetPosition().x ),
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iu2hyp( pad->GetPosition().y ),
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(const char*) ref.c_str(),
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(const char*) padName.c_str(),
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pstackIter->second->GetId() );
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}
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}
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else if( PCB_VIA* via = dyn_cast<PCB_VIA*>( item ) )
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{
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auto pstackIter = m_padMap.find( via );
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if( pstackIter != m_padMap.end() )
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{
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m_out->Print( 1, "(VIA X=%.10f Y=%.10f P=%d)\n",
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iu2hyp( via->GetPosition().x ),
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iu2hyp( via->GetPosition().y ),
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pstackIter->second->GetId() );
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}
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}
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else if( PCB_TRACK* track = dyn_cast<PCB_TRACK*>( item ) )
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{
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const wxString layerName = m_board->GetLayerName( track->GetLayer() );
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m_out->Print( 1, "(SEG X1=%.10f Y1=%.10f X2=%.10f Y2=%.10f W=%.10f L=\"%s\")\n",
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iu2hyp( track->GetStart().x ),
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iu2hyp( track->GetStart().y ),
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iu2hyp( track->GetEnd().x ),
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iu2hyp( track->GetEnd().y ),
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iu2hyp( track->GetWidth() ),
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(const char*) layerName.c_str() );
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}
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else if( PCB_ARC* arc = dyn_cast<PCB_ARC*>( item ) )
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{
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const wxString layerName = m_board->GetLayerName( arc->GetLayer() );
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VECTOR2I start = arc->GetStart();
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VECTOR2I end = arc->GetEnd();
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if( arc->IsCCW() )
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std::swap( start, end );
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m_out->Print( 1, "(ARC X1=%.10f Y1=%.10f X2=%.10f Y2=%.10f XC=%.10f YC=%.10f R=%.10f W=%.10f L=\"%s\")\n",
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iu2hyp( start.x ),
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iu2hyp( start.y ),
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iu2hyp( end.x ),
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iu2hyp( end.y ),
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iu2hyp( arc->GetCenter().x ),
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iu2hyp( arc->GetCenter().y ),
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iu2hyp( arc->GetRadius() ),
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iu2hyp( arc->GetWidth() ),
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(const char*) layerName.c_str() );
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}
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else if( ZONE* zone = dyn_cast<ZONE*>( item ) )
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{
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for( PCB_LAYER_ID layer : zone->GetLayerSet().Seq() )
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{
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const wxString layerName = m_board->GetLayerName( layer );
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SHAPE_POLY_SET fill = zone->GetFilledPolysList( layer )->CloneDropTriangulation();
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fill.Simplify( SHAPE_POLY_SET::PM_FAST );
|
|
|
|
for( int i = 0; i < fill.OutlineCount(); i++ )
|
|
{
|
|
const SHAPE_LINE_CHAIN& outl = fill.COutline( i );
|
|
const VECTOR2I p0 = outl.CPoint( 0 );
|
|
|
|
m_out->Print( 1, "{POLYGON T=POUR L=\"%s\" ID=%d X=%.10f Y=%.10f\n",
|
|
(const char*) layerName.c_str(),
|
|
m_polyId,
|
|
iu2hyp( p0.x ),
|
|
iu2hyp( p0.y ) );
|
|
|
|
for( int v = 0; v < outl.PointCount(); v++ )
|
|
{
|
|
m_out->Print( 2, "(LINE X=%.10f Y=%.10f)\n",
|
|
iu2hyp( outl.CPoint( v ).x ),
|
|
iu2hyp( outl.CPoint( v ).y ) );
|
|
}
|
|
|
|
m_out->Print( 2, "(LINE X=%.10f Y=%.10f)\n", iu2hyp( p0.x ), iu2hyp( p0.y ) );
|
|
m_out->Print( 1, "}\n" );
|
|
|
|
for( int h = 0; h < fill.HoleCount( i ); h++ )
|
|
{
|
|
const SHAPE_LINE_CHAIN& holeShape = fill.CHole( i, h );
|
|
const VECTOR2I ph0 = holeShape.CPoint( 0 );
|
|
|
|
m_out->Print( 1, "{POLYVOID ID=%d X=%.10f Y=%.10f\n",
|
|
m_polyId,
|
|
iu2hyp( ph0.x ),
|
|
iu2hyp( ph0.y ) );
|
|
|
|
for( int v = 0; v < holeShape.PointCount(); v++ )
|
|
{
|
|
m_out->Print( 2, "(LINE X=%.10f Y=%.10f)\n",
|
|
iu2hyp( holeShape.CPoint( v ).x ),
|
|
iu2hyp( holeShape.CPoint( v ).y ) );
|
|
}
|
|
|
|
m_out->Print( 2, "(LINE X=%.10f Y=%.10f)\n",
|
|
iu2hyp( ph0.x ),
|
|
iu2hyp( ph0.y ) );
|
|
m_out->Print( 1, "}\n" );
|
|
}
|
|
|
|
m_polyId++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
const std::vector<BOARD_ITEM*> HYPERLYNX_EXPORTER::collectNetObjects( int netcode )
|
|
{
|
|
std::vector<BOARD_ITEM*> rv;
|
|
|
|
auto check =
|
|
[&]( BOARD_CONNECTED_ITEM* item ) -> bool
|
|
{
|
|
if( ( item->GetLayerSet() & LSET::AllCuMask() ).none() )
|
|
return false;
|
|
|
|
if( item->GetNetCode() == netcode || ( netcode < 0 && item->GetNetCode() <= 0 ) )
|
|
return true;
|
|
|
|
return false;
|
|
};
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
if( check( pad ) )
|
|
rv.push_back( pad );
|
|
}
|
|
}
|
|
|
|
for( PCB_TRACK* item : m_board->Tracks() )
|
|
{
|
|
if( check( item ) )
|
|
rv.push_back( item );
|
|
}
|
|
|
|
for( ZONE* zone : m_board->Zones() )
|
|
{
|
|
if( check( zone ) )
|
|
rv.push_back( zone );
|
|
}
|
|
|
|
return rv;
|
|
}
|
|
|
|
|
|
bool HYPERLYNX_EXPORTER::writeNets()
|
|
{
|
|
m_polyId = 1;
|
|
|
|
for( const NETINFO_ITEM* netInfo : m_board->GetNetInfo() )
|
|
{
|
|
int netcode = netInfo->GetNetCode();
|
|
bool isNullNet = netInfo->GetNetCode() <= 0 || netInfo->GetNetname().IsEmpty();
|
|
|
|
if( isNullNet )
|
|
continue;
|
|
|
|
const std::vector<BOARD_ITEM*> netObjects = collectNetObjects( netcode );
|
|
|
|
if( netObjects.size() )
|
|
{
|
|
m_out->Print( 0, "{NET=\"%s\"\n", (const char*) netInfo->GetNetname().c_str() );
|
|
writeNetObjects( netObjects );
|
|
m_out->Print( 0, "}\n\n" );
|
|
}
|
|
}
|
|
|
|
const std::vector<BOARD_ITEM*> nullNetObjects = collectNetObjects( -1 );
|
|
|
|
int idx = 0;
|
|
|
|
for( BOARD_ITEM* item : nullNetObjects )
|
|
{
|
|
m_out->Print( 0, "{NET=\"EmptyNet%d\"\n", idx );
|
|
writeNetObjects( { item } );
|
|
m_out->Print( 0, "}\n\n" );
|
|
idx++;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool HYPERLYNX_EXPORTER::Run()
|
|
{
|
|
LOCALE_IO toggle; // toggles on, then off, the C locale.
|
|
|
|
try
|
|
{
|
|
m_out.reset( new FILE_OUTPUTFORMATTER( m_outputFilePath.GetFullPath() ) );
|
|
|
|
generateHeaders();
|
|
writeBoardInfo();
|
|
writeStackupInfo();
|
|
writeDevices();
|
|
writePadStacks();
|
|
writeNets();
|
|
}
|
|
catch( IO_ERROR& )
|
|
{
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool ExportBoardToHyperlynx( BOARD* aBoard, const wxFileName& aPath )
|
|
{
|
|
HYPERLYNX_EXPORTER exporter;
|
|
exporter.SetBoard( aBoard );
|
|
exporter.SetOutputFilename( aPath );
|
|
return exporter.Run();
|
|
}
|