This also removes the GROUP/UNGROUP-specific undo actions.
This also fixes a bunch of undo bugs when duplicating
group members, creating pins, etc.
This also fixes some undo bugs when dividing wires etc.
This also fixes some bugs with new sch items not
being created within an entered group.
When building a net tie, all elements in the footprint that belong to
the net tie can be arbitrarily close to one another. outside of the
footprint, connected items can be arbitrarily close to the tie element
but must respect the clearance values for elements that have nets
assigned to them
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19933
(cherry picked from commit bff819edb08e3d303c695b79f990374d259e4d0a)
This means that you can run just a single case from the command line,
for example:
`qa_pcbnew -t DRCCopperSliver/_0`
The case is also automatically printed as context.
This means that when isolating a specific defect in one case,
you can run only that one case, which is useful under debuggers
and also when using slow tools like valgrind.
Not all possibe tests are doing this, but they're easy to do
when needed (i.e. when you want to run just one case)
Recommendation is to avoid using the year nomenclature as this
information is already encoded in the git repo. Avoids needing to
repeatly update.
Also updates AUTHORS.txt from current repo with contributor names
Previously, these checks injected a custom handler to add graphic
objects to a DRC marker. This was not thread-safe and was causing
non-deterministic crashes. The DRC reporting methods now accept
a customer handler which is called on the newly created
PCB_MARKER within the commit context. This defaults to nullptr
for DRC checks which do not require graphics or other additional
processing.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19282
CHANGED: PCB file format now supports saving/loading complex padstacks
CHANGED: PTH pads are now rendered per copper layer in the copper color;
the PTH pad color is no longer used.
ADDED: support for importing complex pad stacks from Altium PCBs
Enforce padstack-aware access to pad properties across KiCad
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8182
We were calculating the same thing in three locations and we missed
adding the clearance from the footprints in, resulting in bad fills and
missed drc errors (see QA addition)
The RegressionZoneFillTests handle issues that are resolved by the zone
filler, so Clipper2 problematic fill belongs there. Otherwise, the
remaining tests should not refill the zones before running DRC because
we expect the DRC to catch errors without needing a refill
