246 Commits

Author SHA1 Message Date
JamesJCode
3a007b8dd7 Remove group_matched token from DRC skew rule
This is the default behaviour anyway
2024-07-30 14:41:06 +01:00
JamesJCode
5187ea721d Implement within_diff_pairs and group_matched DRC skew arguments
Enables DRC to calculate skew based on new arguments to skew
constraint DRC clauses:

Using (group_matched): calculate skew across all matching nets
Using (within_diff_pairs): calculate skew within every diff pair
   found within the matching nets

Additionally fixes DRC skew calculation to calculate skew relative
to the longest net in the skew check set (in line with PNS meander
placer calculations).
2024-07-29 15:28:39 +01:00
James J
7ce00e511b Multi-netclass support 2024-07-26 20:49:29 +00:00
JamesJCode
559854ec0f Add ERC check for dangling wire endpoints 2024-07-22 23:16:08 +01:00
JamesJCode
96977d44d9 Add ERC check for local and global labels with same name
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9461
2024-07-21 23:45:02 +01:00
Seth Hillbrand
16f41a832c Fix issue with model parsing
Sometimes we don't get the data elements in order.  Use the stream name
to ensure we have the correct model.

Also give the parser a bit more memory to work with, avoiding unneeded
resizes
2024-07-16 17:39:49 -07:00
CraftedNightmare
ee78f3bf5b Changed ERC Label caps check to check Power Symbols
Power symbols are implicit labels in KiCad, so we should check for their
caps difference against other power symbols as well as against other
labels

Fixes https://gitlab.com/kicad/code/kicad/-/issues/16897
2024-07-11 18:45:35 +00:00
Seth Hillbrand
845130ba9e ADDED: pcbnew fill avoids kissing fills
Previously, fills could end up just barely touching, leading to DRC
errors even if there was enough room to fill the remaining space.  This
was due to how we shrink/expand the zones to remove small features.  By
adding a zero-width line between points that should be connected, we
expand back to the correct width.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/14130
2024-07-10 18:34:41 -07:00
Seth Hillbrand
4431246cbe ADDED: ERC Test for labels on multiple wires
When a label overlaps two or more wires, it is not clear which one it
should connect to.  This is an ERC warning

Fixes https://gitlab.com/kicad/code/kicad/-/issues/18346
2024-07-09 10:06:27 -07:00
Seth Hillbrand
234230801f Fixup Altium QA.
Apparently, Footprint export does not export the internal rule area
layers.  Saving directly does
2024-06-27 16:38:58 -07:00
Seth Hillbrand
51eb7aa5b5 Fixup for Altium pad/fill importer
The previous commit merged pads with copper areas.  This was appealing
but broke when the pad and the area were meant to have different
size/shape technical layers.  Small pads = Small paste.  Instead, we do
not merge the pads but we assign them to have the appropriate nets in
KiCad, allowing the same effective result but keeping the technical
layers correct
2024-06-27 13:49:16 -07:00
Seth Hillbrand
bcf6b620a8 Large rework of BEZIER_POLY
Add direct handling of quadratic beziers to save compute time and number
of points.  Update cubic interpolation to reduce number of points
generated for a given smoothness

Cache data on open and used cached data to avoid multiple re-calcs

Remove minimum line length and number of segments and replace with
standard max error level.  Allows us to specify the tolerance of bezier
interpolation
2024-06-18 17:55:41 -07:00
Seth Hillbrand
3e16359b4f Update golden master for Altium import
The altium footprint being imported has vias that were ignored before,
so now we need to have the correct golden master with vias
2024-06-14 17:41:44 -07:00
Jon Evans
5fc0f1f51e ADDED: Independent control of front/back via tenting 2024-06-11 21:50:25 -04:00
Jon Evans
4aab9f59aa ADDED: Support tenting control of individual vias
REMOVED: Tenting option from plot dialog (tenting is now
         controlled from Board Setup and via properties)

See https://gitlab.com/kicad/code/kicad/-/issues/2402
2024-06-11 21:25:02 -04:00
Jeff Young
aa1fb0604a Fix KeepUpright settings in Eagle gold files. 2024-06-09 23:38:54 +01:00
Alex Shvartzkop
ee8b74d688 QA: update golden data for Altium "Tracks" PcbLib.
(cherry picked from commit c6b483acb96f0b336a54523c1b290a6818daa550)
2024-06-09 23:03:33 +03:00
Jon Evans
f5e7c705db Move custom shapes to PADSTACK; support in API 2024-06-08 14:26:36 -04:00
Jon Evans
0b0a37aaf7 Move padstack serialization to PADSTACK
Also move a few more things from pad/via
2024-06-04 09:28:24 -04:00
Jeff Young
855c972156 Add regression test and example rule.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18142
2024-06-04 10:58:52 +01:00
Seth Hillbrand
75ab3d9e8b Handle arcs dp coupling
Calculate coupled arcs and spacing

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17967
2024-05-30 16:11:12 -07:00
Jeff Young
a0a368f47b Fix bogus value field in spice test source. 2024-05-10 15:58:48 +01:00
Seth Hillbrand
8463bd59b7 ADDED: Optional check for four way junctions
Defaults to off because this is likely contentious

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17870
2024-05-03 12:06:24 -07:00
dsa-t
16f3237983 QA: update Altium footprint library golden file.
(cherry picked from commit dd2f15c96dd2b9f120d28199fda6a596e21e60a4)

Co-authored-by: Alex Shvartzkop <dudesuchamazing@gmail.com>
2024-04-27 20:35:00 +00:00
Jeff Young
c59ed0bbb7 Flip symbol editor's Y axis to match other editors. 2024-04-27 13:47:56 +01:00
James J
be8744176c Add SCH_RULE_AREA shapes to eeschema
Includes:
 - Fix GAL to draw closed polygons in eeschema
 - Add functionality to eeschema to draw arbitary polygons
 - Update polygon item previews to have customisable edge colour
 - Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
 - Add SCH_RULE_AREA to paint and plot methods
 - Add new rule area color preference to themes
2024-04-25 14:24:46 +00:00
Seth Hillbrand
f61d400d88 Allow non-identical schematic/pcb nets
The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest.  This breaks
the schematic parity check as we have modified the netname for some
pads.  To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
2024-04-15 17:54:44 -07:00
Seth Hillbrand
a9f35ba42e Fix incremental connectivity
The connectivity routine would consider symbols, overwriting unused
subgraphs for pins that were not in the change list.  This is resolved
by updating the full connectivity to only use pins in the graph since
symbols are not connected independently.

In the process of adding QA tests for this change, additional issues
with the schematic QA were discovered.  Specifically, we were not
properly setting the root sheet UUID.  This was partially masked by a
const_cast setting of the RefDes in sch_symbol when called the RefDes
getter.  This exposed the fact that our QA ERC numbers did not match the
schematic editor stand alone ERC numbers.  So the test value for one
check needed to be updated

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17528
2024-04-10 17:25:58 -07:00
Jon Evans
1dbe78c68b Add QA tests and expand serialization for API 2024-04-02 19:51:18 -04:00
Seth Hillbrand
553e4a25bf Tidy up some remaining triangulation cases
Found and fixed a few corner cases where triangulation point removal
could reset expected points
2024-04-01 11:48:12 -07:00
Seth Hillbrand
c3f6a84d66 Update triangulation to handle poly-intersection
Polygon intersections happen against the original outline, not against
the currently remaining polygon.  This avoids pathalogical cases

Adds new simplification system to avoid duplicated points
Adds new edge-splitting algorithm to provide additional fall-back
Verifies that polygon cuts do not swap holes for outlines (negative
area)

Fixes https://gitlab.com/kicad/code/kicad/-/issues/17559
2024-03-28 10:16:24 -07:00
Seth Hillbrand
6b915049d1 Check singular arcs connection
Even if there are no other segments in the line chain, we still should
check for arc connections in cases of individual arcs on a line chain
2024-03-22 10:41:42 -07:00
Mike Williams
543343b7d1 prettifier: add newlines to golden samples 2024-03-18 16:03:09 -04:00
JamesJ
2311eed08a Add new ERC rule to check for global labels with only one entry in the schematic
By default this rule is set to ignore to provide continuity for those using
single global labels to name nets (e.g. in simulation)

Fixes https://gitlab.com/kicad/code/kicad/-/issues/13212
2024-03-17 23:24:43 +00:00
Jon Evans
96ea1f6f89 Revert change to prettifier QA data
The file format should not be bumped in these test cases, they are not a test of the file format writer.
2024-02-25 12:50:44 -05:00
Jeff Young
ee3be0802c Move PCBNew overrides to nullable properties.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/5562
2024-02-24 20:05:51 +00:00
Jeff Young
27c253780d Separate out Pad_Shape so auto-complete can work. 2024-01-10 19:22:05 +00:00
Jon Evans
104aa1abe4 Change prettifier QA to not depend on file format changes
Instead of writing out and reading back in using the plugin,
just test the formatter itself.

Also add support for testing full boards.
2024-01-01 13:38:16 -05:00
jean-pierre charras
58b7eda47a QA test( test_prettifier) update golden files and fix a warning message. 2024-01-01 10:57:32 +01:00
John Beard
751c88ef20 Use 'uuid' (not 'id') in the s-expr PCB groups/generator format
Add some regression tests to check loading of groups and generators
from various versions of the s-expr PCB format.
2023-12-31 23:09:26 +00:00
Jon Evans
ea0673e7a0 Do not merge buses of distinct types
Previously, this code would merge a vector bus
with a group bus containing the vector as a member.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/16439
2023-12-30 10:54:24 -05:00
Jon Evans
2ecf1ac23f Change regression test for #13162 to be less complex
We are really only testing that `Rload1` works,
and the original testcase is unstable on some platforms.
2023-12-29 13:18:46 -05:00
Ian McInerney
d8b47d18d3 Initial rename of file plugin infrastructure components to IO 2023-12-24 01:22:21 +00:00
jean-pierre charras
8e647c24b4 QA test, prettifier: Update golden files to the latest version.
Add also a warning when a golden file is too old and creates comparison error.
2023-12-16 10:49:23 +01:00
John Beard
e41f5efb03 Use modern bool style for footprint locking (locked yes)
Add some simple tests for specific footprint load/save checks
(including round-trip stability)
2023-12-14 21:22:59 +00:00
John Beard
481fa1f959 Allow PCB reference image locking and UUID to be saved
Add some unit tests for reference image saving/loading.

Fixes: https://gitlab.com/kicad/code/kicad/-/issues/16334
2023-12-14 21:22:59 +00:00
Seth Hillbrand
343828c552 Fix invalid string compare in IBIS parser
strcmp returns 0 if strings are the same but compareIbisWord returns
True (1).

Adds an IBIS simulation QA test case to catch this in the future

Fixes https://gitlab.com/kicad/code/kicad/-/issues/16223

(cherry picked from commit ef8b6bf9e1663dfc4af9f24137172f5a219dd42d)
2023-11-30 09:16:38 -08:00
Jon Evans
ae66ce68b5 Update testcases for generator_version 2023-11-29 16:17:41 +00:00
Jon Evans
f1f8981395 Automatic whitespace and indentation prettification for sexpr formats 2023-11-29 16:17:41 +00:00
Seth Hillbrand
9e48b388fe Add additional QA sliver check 2023-11-28 16:02:39 -08:00