Following changes to the `A.NetClass == '<netclass>'` semantics to
match on exact netclass name OR any constituent netclass names, we
can have conditions where constituent netclass constraints match
before the composite netclass constraints in the DRC engine. This
adds the functionality to match on the exact full netclass name, and
modifies the implicit netclass DRC rules to use this function in
their rule condition.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/20797
(cherry picked from commit c25264528c1caae08fb111c8a3bfd2e66283e11e)
- Adds time and delay units
- Adds time domain tuning parameters entry and storage
- Adds pad-to-die delay property
- Adds time domain parameter interface for length / delay calculations
- Adds unit tracking for numerical constants through LIBEVAL
- Will need future work to truly propagate through binary expressions
- Adds time domain tuning to meander placers
- Adds time delay display to net inspector panel
- Modifies DRC to handle time domain constraints
When building a net tie, all elements in the footprint that belong to
the net tie can be arbitrarily close to one another. outside of the
footprint, connected items can be arbitrarily close to the tie element
but must respect the clearance values for elements that have nets
assigned to them
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19933
(cherry picked from commit bff819edb08e3d303c695b79f990374d259e4d0a)
There are two netclass name methods, which previously were not
obvious in their uses. These have been renamed to now have:
GetName() : Used for internal or tooling (e.g. netlist export) usage
GetHumanReadableName() : Used for display to users (e.g. in infobars)
Fixing the previous unclear naming will result in fewer bugs
when users start using the multiple netclass functionality, as
the incorrect usage had started creeping in to new code. Also this
will help authors of new code select the correct name method.
KeepRefreshing is gated so if we get a bunch of phases in a row, they
won't be shown until you get past a slower phase. By yielding here, we
ensure that the dialog is updated and the user knows which phase of DRC
they are on.
Having thread pool as its own singleton in the library meant that each
kiface had its own threadpool, leading to many multiples of the threads
being started. Placing a singleton class in PGM_BASE ensures that all
kifaces use the same thread pool.
The singleton class can be extended to provide single instance
guarantee for any element across kifaces
Recommendation is to avoid using the year nomenclature as this
information is already encoded in the git repo. Avoids needing to
repeatly update.
Also updates AUTHORS.txt from current repo with contributor names
Previously, these checks injected a custom handler to add graphic
objects to a DRC marker. This was not thread-safe and was causing
non-deterministic crashes. The DRC reporting methods now accept
a customer handler which is called on the newly created
PCB_MARKER within the commit context. This defaults to nullptr
for DRC checks which do not require graphics or other additional
processing.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19282
Remove the PROFILE definitions from the incremental connectivity
profiling so a special build isn't required. If the starting and
stopping the profile timer is excessive, we can add this back.
(cherry picked from commit 8a09e5f3c3ab185671a5944625e5f8b3ef4fb5c5)
Items that are part of net ties (pads and copper shapes that connect to
them) should allow connections from any net in the tie. This prevents
clearance errors from being generated for matched nets
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14008
- Implements component classes for placement rule areas and multichannel tool
- Implements property inspector properties for rule areas
- Fixes some zone member default initialisation issues
- Gates all multichannel-related imlpementation with existing adv config flag
- Removes rule area type enum, replaces with inference from keepout and
placement settings
hole_to_hole clearance should account for all holes in the board.
Previously, we had excluded non through holes from this test but that
omits via holes that can still foul a future drill hit.
Designers wanting the old behavior can explicitly set the hole_to_hole
clearance to 0mm for specific ViaType pairs
