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Be consistent about getting board copper layers.

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This commit is contained in:
Jeff Young 2025-07-09 11:08:31 +01:00
parent f097fbdfcc
commit d2a623719b
20 changed files with 47 additions and 58 deletions
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3
pcbnew/dialogs/dialog_pad_properties.cpp
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@ -1967,8 +1967,7 @@ bool DIALOG_PAD_PROPERTIES::transferDataToPad( PAD* aPad )
case 1:
// Front, back and connected
padLayerMask |= LSET::AllCuMask();
aPad->Padstack().SetUnconnectedLayerMode(
PADSTACK::UNCONNECTED_LAYER_MODE::REMOVE_EXCEPT_START_AND_END );
aPad->Padstack().SetUnconnectedLayerMode( PADSTACK::UNCONNECTED_LAYER_MODE::REMOVE_EXCEPT_START_AND_END );
break;
case 2:

4
pcbnew/drc/drc_cache_generator.cpp
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@ -137,7 +137,7 @@ bool DRC_CACHE_GENERATOR::Run()
PCB_DIMENSION_T
};
forEachGeometryItem( itemTypes, LSET::AllCuMask(), countItems );
forEachGeometryItem( itemTypes, boardCopperLayers, countItems );
std::future<void> retn = tp.submit(
[&]()
@ -147,7 +147,7 @@ bool DRC_CACHE_GENERATOR::Run()
if( !m_board->m_CopperItemRTreeCache )
m_board->m_CopperItemRTreeCache = std::make_shared<DRC_RTREE>();
forEachGeometryItem( itemTypes, LSET::AllCuMask(), addToCopperTree );
forEachGeometryItem( itemTypes, boardCopperLayers, addToCopperTree );
} );
std::future_status status = retn.wait_for( std::chrono::milliseconds( 250 ) );

2
pcbnew/drc/drc_test_provider_connection_width.cpp
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@ -307,7 +307,7 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run()
return false; // DRC cancelled
BOARD* board = m_drcEngine->GetBoard();
LSET copperLayerSet = board->GetEnabledLayers() & LSET::AllCuMask();
LSET copperLayerSet = LSET::AllCuMask( board->GetCopperLayerCount() );
LSEQ copperLayers = copperLayerSet.Seq();
int epsilon = board->GetDesignSettings().GetDRCEpsilon();

6
pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp
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@ -460,7 +460,8 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
{
m_board = m_drcEngine->GetBoard();
int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
std::map<DIFF_PAIR_KEY, DIFF_PAIR_ITEMS> dpRuleMatches;
@ -520,8 +521,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run()
m_board->GetConnectivity()->GetFromToCache()->Rebuild( m_board );
forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T }, LSET::AllCuMask(),
evaluateDpConstraints );
forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T }, boardCopperLayers, evaluateDpConstraints );
// drc_dbg( 10, wxT( "dp rule matches %d\n" ), (int) dpRuleMatches.size() );

5
pcbnew/drc/drc_test_provider_matched_length.cpp
View File

@ -351,6 +351,7 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
return false;
}
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
std::map<DRC_RULE*, std::set<BOARD_CONNECTED_ITEM*> > itemSets;
std::shared_ptr<FROM_TO_CACHE> ftCache = m_board->GetConnectivity()->GetFromToCache();
@ -361,14 +362,14 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
size_t count = 0;
size_t ii = 0;
forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(),
forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, boardCopperLayers,
[&]( BOARD_ITEM *item ) -> bool
{
count++;
return true;
} );
forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(),
forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, boardCopperLayers,
[&]( BOARD_ITEM *item ) -> bool
{
if( !reportProgress( ii++, count, progressDelta ) )

24
pcbnew/drc/drc_test_provider_physical_clearance.cpp
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@ -79,7 +79,8 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
m_board = m_drcEngine->GetBoard();
m_itemTree.clear();
int errorMax = m_board->GetDesignSettings().m_MaxError;
int errorMax = m_board->GetDesignSettings().m_MaxError;
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
if( m_board->m_DRCMaxPhysicalClearance <= 0 )
{
@ -139,7 +140,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd );
if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) )
layers |= LSET::AllCuMask();
layers |= boardCopperLayers;
}
else if( item->Type() == PCB_FOOTPRINT_T )
{
@ -246,8 +247,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
// Generate a count for progress reporting.
//
forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T },
LSET::AllCuMask(),
forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, boardCopperLayers,
[&]( BOARD_ITEM* item ) -> bool
{
ZONE* zone = dynamic_cast<ZONE*>( item );
@ -255,7 +255,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
if( zone && zone->GetIsRuleArea() )
return true; // Continue with other items
count += ( item->GetLayerSet() & LSET::AllCuMask() ).count();
count += ( item->GetLayerSet() & boardCopperLayers ).count();
return true;
} );
@ -264,8 +264,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
// Run clearance checks -within- polygonal items.
//
forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T },
LSET::AllCuMask(),
forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, boardCopperLayers,
[&]( BOARD_ITEM* item ) -> bool
{
PCB_SHAPE* shape = dynamic_cast<PCB_SHAPE*>( item );
@ -593,10 +592,8 @@ void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer( ZONE* aZone, PCB_LAYER
}
int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem,
SHAPE* aItemShape,
PCB_LAYER_ID aLayer,
BOARD_ITEM* aOther )
int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem, SHAPE* aItemShape,
PCB_LAYER_ID aLayer, BOARD_ITEM* aOther )
{
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
@ -605,6 +602,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem
int actual;
int violations = 0;
VECTOR2I pos;
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
std::shared_ptr<SHAPE> otherShapeStorage = aOther->GetEffectiveShape( aLayer );
SHAPE* otherShape = otherShapeStorage.get();
@ -659,7 +657,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem
layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd );
if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) )
layers |= LSET::AllCuMask();
layers |= boardCopperLayers;
wxCHECK_MSG( layers.Contains( aLayer ), violations,
wxT( "Bug! Vias should only be checked for layers on which they exist" ) );
@ -682,7 +680,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem
layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd );
if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) )
layers |= LSET::AllCuMask();
layers |= boardCopperLayers;
wxCHECK_MSG( layers.Contains( aLayer ), violations,
wxT( "Bug! Vias should only be checked for layers on which they exist" ) );

3
pcbnew/drc/drc_test_provider_sliver_checker.cpp
View File

@ -78,8 +78,7 @@ bool DRC_TEST_PROVIDER_SLIVER_CHECKER::Run()
double angleTolerance = ADVANCED_CFG::GetCfg().m_SliverAngleTolerance;
double cosangleTol = 2.0 * cos( DEG2RAD( angleTolerance ) );
LSET copperLayerSet = m_drcEngine->GetBoard()->GetEnabledLayers() & LSET::AllCuMask();
LSEQ copperLayers = copperLayerSet.Seq();
LSEQ copperLayers = LSET::AllCuMask( m_drcEngine->GetBoard()->GetCopperLayerCount() ).Seq();
int layerCount = copperLayers.size();
// Report progress on board zones only. Everything else is in the noise.

1
pcbnew/exporters/export_d356.cpp
View File

@ -56,6 +56,7 @@ static int compute_pad_access_code( BOARD *aPcb, LSET aLayerMask )
{
// Non-copper is not interesting here
aLayerMask &= LSET::AllCuMask();
if( !aLayerMask.any() )
return -1;

5
pcbnew/exporters/export_hyperlynx.cpp
View File

@ -103,8 +103,7 @@ public:
bool IsEmpty() const
{
LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers();
LSET outLayers = m_layers & layerMask;
LSET outLayers = m_layers & LSET::AllCuMask( m_board->GetCopperLayerCount() );
return outLayers.none();
}
@ -256,7 +255,7 @@ bool HYPERLYNX_EXPORTER::generateHeaders()
void HYPERLYNX_EXPORTER::writeSinglePadStack( HYPERLYNX_PAD_STACK& aStack )
{
LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers();
LSET layerMask = LSET::AllCuMask( m_board->GetCopperLayerCount() );
LSET outLayers = aStack.m_layers & layerMask;
if( outLayers.none() )

4
pcbnew/exporters/gen_drill_report_files.cpp
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@ -424,11 +424,9 @@ bool GENDRILL_WRITER_BASE::GenDrillReportFile( const wxString& aFullFileName )
out.Print( 0, "Copper Layer Stackup:\n" );
out.Print( 0, separator );
LSET cu = m_pcb->GetEnabledLayers() & LSET::AllCuMask();
int conventional_layer_num = 1;
for( PCB_LAYER_ID layer : cu.UIOrder() )
for( PCB_LAYER_ID layer : LSET::AllCuMask( m_pcb->GetCopperLayerCount() ).UIOrder() )
{
out.Print( 0, " L%-2d: %-25s %s\n",
conventional_layer_num++,

2
pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp
View File

@ -1031,7 +1031,7 @@ PAD* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadPad( const COMPONENT_PAD& aCadstarPad,
break;
case PAD_SIDE::THROUGH_HOLE:
padLayerSet = LSET::AllCuMask() | LSET( { F_Mask, B_Mask, F_Paste, B_Paste } );
padLayerSet = LSET::AllCuMask( m_numCopperLayers ) | LSET( { F_Mask, B_Mask, F_Paste, B_Paste } );
break;
default:

4
pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp
View File

@ -1436,9 +1436,7 @@ void PCB_IO_KICAD_SEXPR::formatLayers( LSET aLayerMask, bool aEnumerateLayers )
static const LSET crt_yd( { B_CrtYd, F_CrtYd } );
static const LSET fab( { B_Fab, F_Fab } );
LSET cu_board_mask = LSET::AllCuMask( m_board
? m_board->GetCopperLayerCount()
: MAX_CU_LAYERS );
LSET cu_board_mask = LSET::AllCuMask( m_board ? m_board->GetCopperLayerCount() : MAX_CU_LAYERS );
std::string output;

7
pcbnew/pcb_io/odbpp/odb_entity.cpp
View File

@ -1155,10 +1155,9 @@ void ODB_STEP_ENTITY::MakeLayerEntity()
for( PCB_LAYER_ID layer : pad_layers )
{
bool onCopperLayer = ( LSET::AllCuMask() & LSET( { layer } ) ).any();
bool onSolderMaskLayer = ( LSET( { F_Mask, B_Mask } ) & LSET( { layer } ) ).any();
bool onSolderPasteLayer =
( LSET( { F_Paste, B_Paste } ) & LSET( { layer } ) ).any();
bool onCopperLayer = LSET::AllCuMask().test( layer );
bool onSolderMaskLayer = LSET( { F_Mask, B_Mask } ).test( layer );
bool onSolderPasteLayer = LSET( { F_Paste, B_Paste } ).test( layer );
if( onSolderMaskLayer )
margin.x = margin.y = pad->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS );

3
pcbnew/pcb_plot_params.cpp
View File

@ -96,8 +96,7 @@ PCB_PLOT_PARAMS::PCB_PLOT_PARAMS()
m_widthAdjust = 0.;
m_textMode = PLOT_TEXT_MODE::DEFAULT;
m_outputDirectory.clear();
m_layerSelection = LSET( { F_SilkS, B_SilkS, F_Mask, B_Mask,
F_Paste, B_Paste, Edge_Cuts } )
m_layerSelection = LSET( { F_SilkS, B_SilkS, F_Mask, B_Mask, F_Paste, B_Paste, Edge_Cuts } )
| LSET::AllCuMask();
m_PDFFrontFPPropertyPopups = true;

2
pcbnew/pcb_track.cpp
View File

@ -1651,7 +1651,7 @@ std::vector<int> PCB_VIA::ViewGetLayers() const
LSET cuMask = LSET::AllCuMask();
if( const BOARD* board = GetBoard() )
cuMask = board->GetEnabledLayers();
cuMask &= board->GetEnabledLayers();
for( PCB_LAYER_ID layer : layers )
{

2
pcbnew/specctra_import_export/specctra.cpp
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@ -80,7 +80,7 @@ void SPECCTRA_DB::buildLayerMaps( BOARD* aBoard )
// specctra wants top physical layer first, then going down to the
// bottom most physical layer in physical sequence.
LSET layerset = aBoard->GetEnabledLayers() & LSET::AllCuMask();
LSET layerset = LSET::AllCuMask( aBoard->GetCopperLayerCount() );
int pcbLayer = 0;
for( PCB_LAYER_ID kiLayer : layerset.CuStack() )

14
pcbnew/specctra_import_export/specctra_export.cpp
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@ -248,9 +248,9 @@ PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, PAD* aPad )
uniqifier = '[';
const int copperCount = aBoard->GetCopperLayerCount();
static const LSET all_cu = LSET::AllCuMask( copperCount );
int reportedLayers = 0;
const int copperCount = aBoard->GetCopperLayerCount();
static const LSET all_cu = LSET::AllCuMask( copperCount );
int reportedLayers = 0;
std::vector<std::string> layerName( copperCount );
bool onAllCopperLayers = ( (aPad->GetLayerSet() & all_cu) == all_cu );
@ -258,7 +258,7 @@ PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, PAD* aPad )
if( onAllCopperLayers )
uniqifier += 'A'; // A for all layers
for( int layer=0; layer<copperCount; ++layer )
for( int layer=0; layer < copperCount; ++layer )
{
PCB_LAYER_ID kilayer = m_pcbLayer2kicad[layer];
@ -889,7 +889,7 @@ IMAGE* SPECCTRA_DB::makeIMAGE( BOARD* aBoard, FOOTPRINT* aFootprint )
// Now, build keepout polygon on each copper layer where the zone
// keepout is living (keepout zones can live on many copper layers)
LSET layerset = aBoard->GetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask();
LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() );
for( PCB_LAYER_ID layer : layerset.CuStack() )
{
@ -1215,7 +1215,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
// Now, build zone polygon on each copper layer where the zone
// is living (zones can live on many copper layers)
LSET layerset = aBoard->GetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask();
LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() );
for( PCB_LAYER_ID layer : layerset )
{
@ -1339,7 +1339,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
// Now, build keepout polygon on each copper layer where the zone
// keepout is living (keepout zones can live on many copper layers)
LSET layerset = aBoard->GetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask();
LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() );
for( PCB_LAYER_ID layer : layerset )
{

8
pcbnew/tools/pcb_selection_tool.cpp
View File

@ -1544,11 +1544,9 @@ int PCB_SELECTION_TOOL::expandConnection( const TOOL_EVENT& aEvent )
}
void PCB_SELECTION_TOOL::selectAllConnectedTracks(
const std::vector<BOARD_CONNECTED_ITEM*>& aStartItems, STOP_CONDITION aStopCondition )
void PCB_SELECTION_TOOL::selectAllConnectedTracks( const std::vector<BOARD_CONNECTED_ITEM*>& aStartItems,
STOP_CONDITION aStopCondition )
{
const LSET allCuMask = LSET::AllCuMask();
PROF_TIMER refreshTimer;
double refreshIntervalMs = 500; // Refresh display with this interval to indicate progress
int lastSelectionSize = (int) m_selection.GetSize();
@ -1672,7 +1670,7 @@ void PCB_SELECTION_TOOL::selectAllConnectedTracks(
for( int i = (int) activePts.size() - 1; i >= 0; --i )
{
VECTOR2I pt = activePts[i].first;
LSET layerSetCu = activePts[i].second & allCuMask;
LSET layerSetCu = activePts[i].second & LSET::AllCuMask();
auto viaIt = viaMap.find( pt );
auto padIt = padMap.find( pt );

2
pcbnew/tracks_cleaner.cpp
View File

@ -432,7 +432,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment
// Examine the list of connected pads: if a through pad is found, the via is redundant
for( PAD* pad : m_brd->GetConnectivity()->GetConnectedPads( via ) )
{
const LSET all_cu = LSET::AllCuMask();
const LSET all_cu = LSET::AllCuMask( m_brd->GetCopperLayerCount() );
if( ( pad->GetLayerSet() & all_cu ) == all_cu )
{

4
pcbnew/zone_filler.cpp
View File

@ -286,7 +286,7 @@ bool ZONE_FILLER::Fill( const std::vector<ZONE*>& aZones, bool aCheck, wxWindow*
footprint->BuildNetTieCache();
}
LSET boardCuMask = m_board->GetEnabledLayers() & LSET::AllCuMask();
LSET boardCuMask = LSET::AllCuMask( m_board->GetCopperLayerCount() );
auto findHighestPriorityZone =
[&]( const BOX2I& bbox, PCB_LAYER_ID itemLayer, int netcode,
@ -768,7 +768,7 @@ bool ZONE_FILLER::Fill( const std::vector<ZONE*>& aZones, bool aCheck, wxWindow*
// Don't check for connections on layers that only exist in the zone but
// were disabled in the board
BOARD* board = zone->GetBoard();
LSET zoneCopperLayers = zone->GetLayerSet() & LSET::AllCuMask() & board->GetEnabledLayers();
LSET zoneCopperLayers = zone->GetLayerSet() & LSET::AllCuMask( board->GetCopperLayerCount() );
// Min-thickness is the web thickness. On the other hand, a blob min-thickness by
// min-thickness is not useful. Since there's no obvious definition of web vs. blob, we