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DRCEpsilon is generic. Zone knockouts need more specific values.

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Each knockout can be approximated, and each knockout
will have m_ExtraClearance added.  If a neck is
between two knockouts, it will be 2X the above
values narrower than expected.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/20361
This commit is contained in:
Jeff Young 2025-05-04 14:50:35 +01:00
parent ebc86d1fa4
commit 96522c4113
2 changed files with 11 additions and 7 deletions
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14
pcbnew/drc/drc_test_provider_connection_width.cpp
View File

@ -49,6 +49,7 @@
#include <pcb_track.h>
#include <pad.h>
#include <zone.h>
#include <advanced_config.h>
/*
Checks for copper connections that are less than the specified minimum width
@ -317,12 +318,16 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run()
if( !reportPhase( _( "Checking nets for minimum connection width..." ) ) )
return false; // DRC cancelled
LSET copperLayerSet = m_drcEngine->GetBoard()->GetEnabledLayers() & LSET::AllCuMask();
LSEQ copperLayers = copperLayerSet.Seq();
BOARD* board = m_drcEngine->GetBoard();
LSET copperLayerSet = board->GetEnabledLayers() & LSET::AllCuMask();
LSEQ copperLayers = copperLayerSet.Seq();
int epsilon = board->GetDesignSettings().GetDRCEpsilon();
// A neck in a zone fill will be DRCEpsilon smaller on *each* side
// Zone knockouts can be approximated, and always have extra clearance built in
epsilon += board->GetDesignSettings().m_MaxError + pcbIUScale.mmToIU( ADVANCED_CFG::GetCfg().m_ExtraClearance );
// A neck in a zone fill can be between two knockouts. In this case it will be epsilon smaller
// on -each- side.
epsilon *= 2;
/*
@ -330,8 +335,7 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run()
* each distinct minWidth, and then decide if any copper which failed that minWidth actually
* was required to abide by it or not.
*/
std::set<int> distinctMinWidths
= m_drcEngine->QueryDistinctConstraints( CONNECTION_WIDTH_CONSTRAINT );
std::set<int> distinctMinWidths = m_drcEngine->QueryDistinctConstraints( CONNECTION_WIDTH_CONSTRAINT );
if( m_drcEngine->IsCancelled() )
return false; // DRC cancelled

4
qa/data/pcbnew/connection_width_rules.kicad_pcb
View File

@ -116,8 +116,8 @@
)
(segment (start 112.5474 77.5716) (end 106.1212 77.5716) (width 0.25) (layer "F.Cu") (net 1) (tstamp 07a05dc9-fd0c-4bac-8cfe-73f661e50f58))
(segment (start 112.7506 77.5716) (end 116.7384 77.5716) (width 0.25) (layer "F.Cu") (net 1) (tstamp b9c8bd88-3577-41fd-b8a3-f84c3ec54539))
(segment (start 112.8014 74.2442) (end 116.7892 74.2442) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5fd40a5e-8558-46fc-9321-fcda035db40b))
(segment (start 112.7556 77.5716) (end 116.7384 77.5716) (width 0.25) (layer "F.Cu") (net 1) (tstamp b9c8bd88-3577-41fd-b8a3-f84c3ec54539))
(segment (start 112.8064 74.2442) (end 116.7892 74.2442) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5fd40a5e-8558-46fc-9321-fcda035db40b))
(segment (start 112.5982 74.2442) (end 106.172 74.2442) (width 0.25) (layer "F.Cu") (net 2) (tstamp 7014ab67-9149-4546-9f6e-d99764e15f97))
(segment (start 112.7252 78.5622) (end 116.713 78.5622) (width 0.25) (layer "F.Cu") (net 3) (tstamp 7c6d2fd8-65cf-4c16-ba39-e8c3cd86d13d))
(segment (start 112.522 78.5622) (end 106.0958 78.5622) (width 0.25) (layer "F.Cu") (net 3) (tstamp a38443b8-d7a2-41c0-b6b5-5218a5114002))