mirror of
https://gitlab.com/kicad/code/kicad.git
synced 2025-09-14 02:03:12 +02:00
Allow soldermask bridging between nettie items
Previously we only allowed graphical items but within the net-tie we need to allow bridging for connected items as well Fixes https://gitlab.com/kicad/code/kicad/-/issues/19288
This commit is contained in:
Seth Hillbrand
parent
54085c4e50
commit
8faf1b4d0e
@ -432,14 +432,27 @@ bool DRC_TEST_PROVIDER_SOLDER_MASK::checkItemMask( BOARD_ITEM* aMaskItem, int aT
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if( fp->AllowSolderMaskBridges() )
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return false;
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// Graphic items are used to implement net-ties between pads of a group within a net-tie
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// footprint. They must be allowed to intrude into their pad's mask aperture.
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if( aTestNet < 0 && aMaskItem->Type() == PCB_PAD_T && fp->IsNetTie() )
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// Items belonging to a net-tie may share the mask aperture of pads in the same group.
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if( aMaskItem->Type() == PCB_PAD_T && fp->IsNetTie() )
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{
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PAD* pad = static_cast<PAD*>( aMaskItem );
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std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
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int groupIdx = padNumberToGroupIdxMap[ pad->GetNumber() ];
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if( padNumberToGroupIdxMap[ static_cast<PAD*>( aMaskItem )->GetNumber() ] >= 0 )
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return false;
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if( groupIdx >= 0 )
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{
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if( aTestNet < 0 )
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return false;
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if( pad->GetNetCode() == aTestNet )
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return false;
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for( PAD* other : fp->GetNetTiePads( pad ) )
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{
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if( other->GetNetCode() == aTestNet )
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return false;
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}
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}
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}
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}
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@ -498,6 +511,22 @@ void DRC_TEST_PROVIDER_SOLDER_MASK::testItemAgainstItems( BOARD_ITEM* aItem, con
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return false;
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}
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if( itemFP && itemFP->IsNetTie() )
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{
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const std::set<int>& nets = itemFP->GetNetTieCache( aItem );
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if( otherNet < 0 || nets.count( otherNet ) )
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return false;
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}
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if( FOOTPRINT* otherFP = other->GetParentFootprint(); otherFP && otherFP->IsNetTie() )
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{
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const std::set<int>& nets = otherFP->GetNetTieCache( other );
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if( itemNet < 0 || nets.count( itemNet ) )
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return false;
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}
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BOARD_ITEM* a = aItem;
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BOARD_ITEM* b = other;
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525
qa/data/pcbnew/net_tie_drc.kicad_pcb
Normal file
525
qa/data/pcbnew/net_tie_drc.kicad_pcb
Normal file
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(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 0 0 -90)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "ac076432-ade5-4f7d-9eea-0befbf91a423")
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Description" "Net tie, 2 pins"
|
||||
(at 0 0 -90)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "5fdb3e89-0980-40b4-8667-2c2d6e6fec09")
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(attr exclude_from_pos_files exclude_from_bom allow_missing_courtyard allow_soldermask_bridges)
|
||||
(net_tie_pad_groups "1, 2")
|
||||
(fp_poly
|
||||
(pts
|
||||
(xy -0.5 -0.25) (xy 0.5 -0.25) (xy 0.5 0.25) (xy -0.5 0.25)
|
||||
)
|
||||
(stroke
|
||||
(width 0)
|
||||
(type solid)
|
||||
)
|
||||
(fill solid)
|
||||
(layer "F.Cu")
|
||||
(uuid "9a9e2914-1292-48cc-aa1d-2d4292da6e54")
|
||||
)
|
||||
(pad "1" smd circle
|
||||
(at -0.5 0 270)
|
||||
(size 0.5 0.5)
|
||||
(layers "F.Cu")
|
||||
(net 2 "B")
|
||||
(pinfunction "1")
|
||||
(pintype "passive")
|
||||
(uuid "16ee3534-48c0-44b3-b649-f8b24a84f4ed")
|
||||
)
|
||||
(pad "2" smd circle
|
||||
(at 0.5 0 270)
|
||||
(size 0.5 0.5)
|
||||
(layers "F.Cu")
|
||||
(net 1 "A")
|
||||
(pinfunction "2")
|
||||
(pintype "passive")
|
||||
(uuid "d3c8b6d3-a993-413b-909d-c43940be048b")
|
||||
)
|
||||
)
|
||||
(gr_rect
|
||||
(start 137.5 90)
|
||||
(end 152 104.5)
|
||||
(stroke
|
||||
(width 0.05)
|
||||
(type default)
|
||||
)
|
||||
(fill none)
|
||||
(layer "Edge.Cuts")
|
||||
(uuid "bead2996-4868-48a3-919e-3743e6296f6b")
|
||||
)
|
||||
(via
|
||||
(at 144.5 94)
|
||||
(size 0.5)
|
||||
(drill 0.3)
|
||||
(layers "F.Cu" "B.Cu")
|
||||
(free yes)
|
||||
(net 2)
|
||||
(uuid "4b8d3731-6cd8-4f67-a659-7cbd9fcf0604")
|
||||
)
|
||||
(zone
|
||||
(net 2)
|
||||
(net_name "B")
|
||||
(layer "B.Cu")
|
||||
(uuid "0a20124f-74b0-4055-a6e6-e87b035a7722")
|
||||
(hatch edge 0.5)
|
||||
(connect_pads
|
||||
(clearance 0.5)
|
||||
)
|
||||
(min_thickness 0.25)
|
||||
(filled_areas_thickness no)
|
||||
(fill yes
|
||||
(thermal_gap 0.5)
|
||||
(thermal_bridge_width 0.5)
|
||||
)
|
||||
(polygon
|
||||
(pts
|
||||
(xy 152 90) (xy 137.5 90) (xy 137.5 104.5) (xy 152 104.5)
|
||||
)
|
||||
)
|
||||
(filled_polygon
|
||||
(layer "B.Cu")
|
||||
(pts
|
||||
(xy 151.442539 90.520185) (xy 151.488294 90.572989) (xy 151.4995 90.6245) (xy 151.4995 103.8755)
|
||||
(xy 151.479815 103.942539) (xy 151.427011 103.988294) (xy 151.3755 103.9995) (xy 138.1245 103.9995)
|
||||
(xy 138.057461 103.979815) (xy 138.011706 103.927011) (xy 138.0005 103.8755) (xy 138.0005 90.6245)
|
||||
(xy 138.020185 90.557461) (xy 138.072989 90.511706) (xy 138.1245 90.5005) (xy 151.3755 90.5005)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
@ -68,6 +68,7 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR
|
||||
"issue17967/issue17967", // Arc dp coupling
|
||||
"issue18203", // DRC error due to colliding arc and circle
|
||||
"unconnected-netnames/unconnected-netnames", // Raised false schematic partity error
|
||||
"net_tie_drc" // Net tie bridging soldermask DRC test
|
||||
};
|
||||
|
||||
for( const wxString& relPath : tests )
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user