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Alex Shvartzkop 2025-07-07 17:43:14 +03:00
parent 7581502453
commit 50e902c06b
41 changed files with 1548 additions and 2774 deletions
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95
translation/pofiles/ar.po
View File

@ -6,7 +6,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-01 16:38+0000\n"
"Last-Translator: Morad Tamer <Morad.TFarouk@gmail.com>\n"
"Language-Team: Arabic <https://hosted.weblate.org/projects/kicad/v9/ar/>\n"
@ -11999,7 +11999,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12446,7 +12446,7 @@ msgid "Hierarchical Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr ""
@ -12458,22 +12458,22 @@ msgstr ""
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -38029,18 +38029,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -38049,7 +38049,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -38057,12 +38057,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -38070,7 +38070,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -38078,7 +38078,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -38087,21 +38087,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -38109,14 +38109,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -38131,7 +38131,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -38140,13 +38140,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -38155,71 +38155,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -38586,18 +38567,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/bg.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-02-27 07:25+0000\n"
"Last-Translator: 109247019824 <109247019824@users.noreply.hosted.weblate."
"org>\n"
@ -13302,7 +13302,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Настройки на не-медните зони"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13813,7 +13813,7 @@ msgid "Hierarchical Label Properties"
msgstr "Настройки на йерархичен етикет"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Настройки на етикет"
@ -13827,12 +13827,12 @@ msgstr "Настройки на йерархичен етикет"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Настройки на извода на йерархическия лист"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Поле %s неможе да бъде празно."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13840,12 +13840,12 @@ msgstr "Поле %s неможе да бъде празно."
msgid "untitled"
msgstr "Количество"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Настройки на етикет"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "Поле %s неможе да бъде празно."
@ -42660,18 +42660,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -42680,7 +42680,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -42688,12 +42688,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -42701,7 +42701,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -42709,7 +42709,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -42718,21 +42718,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -42740,14 +42740,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -42762,7 +42762,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -42771,13 +42771,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -42786,71 +42786,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -43217,18 +43198,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/ca.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-05-11 14:03+0000\n"
"Last-Translator: Adolfo Jayme Barrientos <fitojb@ubuntu.com>\n"
"Language-Team: Catalan <https://hosted.weblate.org/projects/kicad/v9/ca/>\n"
@ -12809,7 +12809,7 @@ msgstr ""
"de la fulla."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13285,7 +13285,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propietats de l'etiqueta jeràrquica"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propietats de l'etiqueta"
@ -13297,11 +13297,11 @@ msgstr "Propietats d'etiqueta directiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propietats del pin del full jeràrquic"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "L'etiqueta no pot estar buida."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13309,12 +13309,12 @@ msgstr "L'etiqueta no pot estar buida."
msgid "untitled"
msgstr "Quantitat"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Propietats de l'etiqueta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "El primer camp és obligatori."
@ -41549,18 +41549,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41569,7 +41569,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41577,12 +41577,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41590,7 +41590,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41598,7 +41598,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41607,21 +41607,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41629,14 +41629,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41651,7 +41651,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41660,13 +41660,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41675,71 +41675,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42106,18 +42087,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/cs.po
View File

@ -21,7 +21,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-22 14:33+0000\n"
"Last-Translator: Jan Straka <bach@email.cz>\n"
"Language-Team: Czech <https://hosted.weblate.org/projects/kicad/v9/cs/>\n"
@ -12300,7 +12300,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Název souboru listu lze změnit pouze v okně Vlastnosti listu."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12756,7 +12756,7 @@ msgid "Hierarchical Label Properties"
msgstr "Vlastnosti hierarchického označení"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Vlastnosti označení"
@ -12768,22 +12768,22 @@ msgstr "Vlastnosti označení direktivy"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Vlastnosti vývodů hierarchického listu"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Označení nemůže být prázdné."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "nepojmenováno"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Upravit Vlastnosti označení"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "První pole je povinné."
@ -39904,18 +39904,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39924,7 +39924,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39932,12 +39932,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39945,7 +39945,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39953,7 +39953,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39962,21 +39962,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39984,14 +39984,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40006,7 +40006,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40015,13 +40015,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40030,71 +40030,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40474,18 +40455,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/da.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-01-23 15:38+0000\n"
"Last-Translator: John Beard <john.j.beard@gmail.com>\n"
"Language-Team: Danish <https://hosted.weblate.org/projects/kicad/master-"
@ -12907,7 +12907,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Viser dialogboksen med elementegenskaber"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -13391,7 +13391,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hierarkiske etiketegenskaber"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Mærkegenskaber"
@ -13404,12 +13404,12 @@ msgstr "Hierarkiske etiketegenskaber"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarkiske egenskaber for arknål"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Netnavnet kan ikke være tomt."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13417,12 +13417,12 @@ msgstr "Netnavnet kan ikke være tomt."
msgid "untitled"
msgstr "Untitled Sheet"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Mærkegenskaber"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "De første %d felter er obligatoriske."
@ -41841,18 +41841,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41861,7 +41861,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41869,12 +41869,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41882,7 +41882,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41890,7 +41890,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41899,21 +41899,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41921,14 +41921,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41943,7 +41943,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41952,13 +41952,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41967,71 +41967,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42398,18 +42379,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

97
translation/pofiles/de.po
View File

@ -29,7 +29,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad i18n Deutsch\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-03 17:15+0000\n"
"Last-Translator: \"Pferd O.\" <frank.0228@ich-war-hier.de>\n"
"Language-Team: German <https://hosted.weblate.org/projects/kicad/v9/de/>\n"
@ -12466,7 +12466,7 @@ msgstr ""
"werden."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12924,7 +12924,7 @@ msgid "Hierarchical Label Properties"
msgstr "Eigenschaften des hierarchischen Bezeichners"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Eigenschaften des Bezeichners"
@ -12936,22 +12936,22 @@ msgstr "Eigenschaften des Anweisungsbezeichners"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Eigenschaften eines hierarchischen Schaltplanpins"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Bezeichner darf nicht leer sein."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "unbenannt"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Bezeichnereigenschaften bearbeiten"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Das erste Feld ist notwendig."
@ -40244,24 +40244,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40270,7 +40271,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40278,12 +40279,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40291,7 +40292,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40299,7 +40300,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40308,21 +40309,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40330,14 +40331,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40352,7 +40353,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40361,13 +40362,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40376,71 +40377,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41057,6 +41039,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -41200,18 +41183,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Weitere Beispiele\n"
"\n"

95
translation/pofiles/el.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-01 11:56+0000\n"
"Last-Translator: aris-kimi <aris_kimi@hotmail.com>\n"
"Language-Team: Greek <https://hosted.weblate.org/projects/kicad/v9/el/>\n"
@ -12671,7 +12671,7 @@ msgstr ""
"φύλλου."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13133,7 +13133,7 @@ msgid "Hierarchical Label Properties"
msgstr "Ιδιότητες Ιεραρχικής Ετικέτας"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Ιδιότητες Ετικέτας"
@ -13145,22 +13145,22 @@ msgstr "Ιδιότητες Ετικέτας Οδηγίας"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Ιδιότητες Ακροδεκτών Ιεραρχικού Φύλλου"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Η ετικέτα δεν μπορεί να είναι κενή."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "χωρίς όνομα"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Επεξεργασία Ιδιοτήτων Ετικέτας"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Το πρώτο πεδίο είναι υποχρεωτικό."
@ -40856,18 +40856,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40876,7 +40876,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40884,12 +40884,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40897,7 +40897,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40905,7 +40905,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40914,21 +40914,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40936,14 +40936,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40958,7 +40958,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40967,13 +40967,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40982,71 +40982,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41738,18 +41719,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Περισσότερα Παραδείγματα\n"
"\n"

326
translation/pofiles/en.po
View File

@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2018-07-15 17:07+0200\n"
"Last-Translator: Simon Richter <Simon.Richter@hogyros.de>\n"
"Language-Team: Simon Richter <Simon.Richter@hogyros.de>\n"
@ -27612,18 +27612,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -27632,7 +27632,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -27640,12 +27640,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -27653,7 +27653,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -27661,7 +27661,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -27670,21 +27670,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -27692,14 +27692,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -27714,7 +27714,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -27723,13 +27723,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -27738,71 +27738,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -27812,18 +27793,18 @@ msgstr ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -27832,7 +27813,7 @@ msgstr ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -27840,12 +27821,12 @@ msgstr ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -27853,7 +27834,7 @@ msgstr ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -27861,7 +27842,7 @@ msgstr ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -27870,21 +27851,21 @@ msgstr ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -27892,14 +27873,14 @@ msgstr ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -27914,7 +27895,7 @@ msgstr ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -27923,13 +27904,13 @@ msgstr ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -27938,71 +27919,52 @@ msgstr ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -28554,18 +28516,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### More Examples\n"
"\n"
@ -28709,18 +28659,6 @@ msgstr ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgid "Default Properties for Round Shapes"
msgstr "Default Properties for Round Shapes"
@ -37301,18 +37239,18 @@ msgstr "KiCad Drawing Sheet"
#~ "| Constraint type | Argument "
#~ "type "
#~ "| "
#~ "Description "
#~ "Description "
#~ "|\n"
#~ "|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
#~ "|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
#~ "| `annular_width` | min/opt/"
#~ "max "
#~ "| Checks the width of annular rings on vias."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `assertion` | \"&lt;"
#~ "expression>\" "
#~ "| Checks the given expression."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `clearance` | "
#~ "min "
@ -37321,7 +37259,7 @@ msgstr "KiCad Drawing Sheet"
#~ "clearance between objects regardless of net.)<br><br>To allow copper "
#~ "objects to overlap (collide), create a `clearance` constraint with the "
#~ "`min` value less than zero (for example, `-1`)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `courtyard_clearance` | "
#~ "min "
@ -37329,13 +37267,13 @@ msgstr "KiCad Drawing Sheet"
#~ "error if any two courtyards are closer than the `min` distance. If a "
#~ "footprint does not have a courtyard shape, no errors will be generated "
#~ "from this constraint."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `creepage` | "
#~ "min "
#~ "| Specifies the creepage distance between copper objects of different "
#~ "nets."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `diff_pair_gap` | min/opt/"
#~ "max "
@ -37343,7 +37281,7 @@ msgstr "KiCad Drawing Sheet"
#~ "tracks are segments that are parallel to each other. Differential pair "
#~ "gap is not tested on uncoupled portions of a differential pair (for "
#~ "example, the fanout from a component)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `diff_pair_uncoupled` | "
#~ "max "
@ -37351,7 +37289,7 @@ msgstr "KiCad Drawing Sheet"
#~ "from the other polarity track in the pair (for example, where the pair "
#~ "fans out from a component, or becomes uncoupled to pass around another "
#~ "object such as a via)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `disallow` | "
#~ "`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -37361,14 +37299,14 @@ msgstr "KiCad Drawing Sheet"
#~ "will be created.<br><br>This constraint is essentially the same as a "
#~ "keepout rule area, but can be used to create more specific keepout "
#~ "restrictions."
#~ "<br> |\n"
#~ "<br> |\n"
#~ "| `edge_clearance` | min/opt/"
#~ "max "
#~ "| Checks the clearance between objects and the board edge.<br><br>This "
#~ "can also be thought of as the \"milling tolerance\" as the board edge "
#~ "will include all graphical items on the `Edge.Cuts` layer as well as any "
#~ "*oval* pad holes. (See `physical_hole_clearance` for the drilling "
#~ "tolerance.)<br> "
#~ "tolerance.)<br> "
#~ "|\n"
#~ "| `length` | min/"
#~ "max "
@ -37376,7 +37314,7 @@ msgstr "KiCad Drawing Sheet"
#~ "condition and generates an error for each net that is below the `min` "
#~ "value (if specified) or above the `max` value (if specified) of the "
#~ "constraint."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole` | min/"
#~ "max "
@ -37384,14 +37322,14 @@ msgstr "KiCad Drawing Sheet"
#~ "holes, the smaller (minor) diameter will be tested against the `min` "
#~ "value (if specified) and the larger (major) diameter will be tested "
#~ "against the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole_clearance` | "
#~ "min "
#~ "| Checks the clearance between a drilled hole in a pad or via and copper "
#~ "objects on a different net. The clearance is measured from the diameter "
#~ "of the hole, not its center."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole_to_hole` | "
#~ "min "
@ -37408,7 +37346,7 @@ msgstr "KiCad Drawing Sheet"
#~ "non-copper layers).<br><br>While this can perform more general-purpose "
#~ "checks than `clearance`, it is much slower. Use `clearance` where "
#~ "possible."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `physical_hole_clearance` | "
#~ "min "
@ -37417,13 +37355,13 @@ msgstr "KiCad Drawing Sheet"
#~ "the hole, not its center.<br><br>This can also be thought of as the "
#~ "\"drilling tolerance\" as it only includes **round** holes (see "
#~ "`edge_clearance` for the milling tolerance)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `silk_clearance` | min/opt/"
#~ "max "
#~ "| Checks the clearance between objects on silkscreen layers and other "
#~ "objects."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `skew` | "
#~ "max "
@ -37432,52 +37370,71 @@ msgstr "KiCad Drawing Sheet"
#~ "the lengths of each net that is matched by the rule. If the absolute "
#~ "value of the difference between that average and the length of any one "
#~ "net is above the constraint `max` value, an error will be generated."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `solder_mask_expansion` | "
#~ "opt "
#~ "| Specifies the solder mask expansion for pads, shapes and "
#~ "tracks. "
#~ "|\n"
#~ "| `solder_paste_abs_margin` | "
#~ "opt "
#~ "| Specifies the absolute solder paste clearance for pads. Usually "
#~ "negative to inset the paste.<br><br>The final solder paste clearace will "
#~ "be the absolute clearance plus the relative "
#~ "clearance. "
#~ "|\n"
#~ "| `solder_paste_rel_margin` | "
#~ "opt "
#~ "| Specifies the relative solder paste clearance for pads. Usually "
#~ "negative to inset the paste.<br><br>The final solder paste clearace will "
#~ "be the absolute clearance plus the relative "
#~ "clearance. "
#~ "|\n"
#~ "| `thermal_relief_gap` | "
#~ "min "
#~ "| Specifies the width of the gap between a pad and a zone with a thermal-"
#~ "relief connection."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `thermal_spoke_width` | "
#~ "opt "
#~ "| Specifies the width of the spokes connecting a pad to a zone with a "
#~ "thermal-relief connection."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_width` | min/opt/"
#~ "max "
#~ "| Checks the width of track and arc segments. An error will be generated "
#~ "for each segment that has a width below the `min` value (if specified) or "
#~ "above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_angle` | min/opt/"
#~ "max "
#~ "| Checks the angle between two connected track segments. An error will "
#~ "be generated for each connected pair with an angle below the `min` value "
#~ "(if specified) or above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_segment_length` | min/"
#~ "max "
#~ "| Checks the length of track and arc segments. An error will be "
#~ "generated for each segment that has a length below the `min` value (if "
#~ "specified) or above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `via_count` | "
#~ "max "
#~ "| Counts the number of vias on every net matched by the rule condition. "
#~ "If that number exceeds the constraint `max` value on any matched net, an "
#~ "error will be generated for that net."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `zone_connection` | "
#~ "`solid`<br>`thermal_reliefs`<br>`none` "
#~ "| Specifies the connection to be made between a zone and a pad."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "\n"
#~ "\n"
@ -37487,18 +37444,18 @@ msgstr "KiCad Drawing Sheet"
#~ "| Constraint type | Argument "
#~ "type "
#~ "| "
#~ "Description "
#~ "Description "
#~ "|\n"
#~ "|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
#~ "|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
#~ "| `annular_width` | min/opt/"
#~ "max "
#~ "| Checks the width of annular rings on vias."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `assertion` | \"&lt;"
#~ "expression>\" "
#~ "| Checks the given expression."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `clearance` | "
#~ "min "
@ -37507,7 +37464,7 @@ msgstr "KiCad Drawing Sheet"
#~ "clearance between objects regardless of net.)<br><br>To allow copper "
#~ "objects to overlap (collide), create a `clearance` constraint with the "
#~ "`min` value less than zero (for example, `-1`)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `courtyard_clearance` | "
#~ "min "
@ -37515,13 +37472,13 @@ msgstr "KiCad Drawing Sheet"
#~ "error if any two courtyards are closer than the `min` distance. If a "
#~ "footprint does not have a courtyard shape, no errors will be generated "
#~ "from this constraint."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `creepage` | "
#~ "min "
#~ "| Specifies the creepage distance between copper objects of different "
#~ "nets."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `diff_pair_gap` | min/opt/"
#~ "max "
@ -37529,7 +37486,7 @@ msgstr "KiCad Drawing Sheet"
#~ "tracks are segments that are parallel to each other. Differential pair "
#~ "gap is not tested on uncoupled portions of a differential pair (for "
#~ "example, the fanout from a component)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `diff_pair_uncoupled` | "
#~ "max "
@ -37537,7 +37494,7 @@ msgstr "KiCad Drawing Sheet"
#~ "from the other polarity track in the pair (for example, where the pair "
#~ "fans out from a component, or becomes uncoupled to pass around another "
#~ "object such as a via)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `disallow` | "
#~ "`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -37547,14 +37504,14 @@ msgstr "KiCad Drawing Sheet"
#~ "will be created.<br><br>This constraint is essentially the same as a "
#~ "keepout rule area, but can be used to create more specific keepout "
#~ "restrictions."
#~ "<br> |\n"
#~ "<br> |\n"
#~ "| `edge_clearance` | min/opt/"
#~ "max "
#~ "| Checks the clearance between objects and the board edge.<br><br>This "
#~ "can also be thought of as the \"milling tolerance\" as the board edge "
#~ "will include all graphical items on the `Edge.Cuts` layer as well as any "
#~ "*oval* pad holes. (See `physical_hole_clearance` for the drilling "
#~ "tolerance.)<br> "
#~ "tolerance.)<br> "
#~ "|\n"
#~ "| `length` | min/"
#~ "max "
@ -37562,7 +37519,7 @@ msgstr "KiCad Drawing Sheet"
#~ "condition and generates an error for each net that is below the `min` "
#~ "value (if specified) or above the `max` value (if specified) of the "
#~ "constraint."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole` | min/"
#~ "max "
@ -37570,14 +37527,14 @@ msgstr "KiCad Drawing Sheet"
#~ "holes, the smaller (minor) diameter will be tested against the `min` "
#~ "value (if specified) and the larger (major) diameter will be tested "
#~ "against the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole_clearance` | "
#~ "min "
#~ "| Checks the clearance between a drilled hole in a pad or via and copper "
#~ "objects on a different net. The clearance is measured from the diameter "
#~ "of the hole, not its center."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `hole_to_hole` | "
#~ "min "
@ -37594,7 +37551,7 @@ msgstr "KiCad Drawing Sheet"
#~ "non-copper layers).<br><br>While this can perform more general-purpose "
#~ "checks than `clearance`, it is much slower. Use `clearance` where "
#~ "possible."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `physical_hole_clearance` | "
#~ "min "
@ -37603,13 +37560,13 @@ msgstr "KiCad Drawing Sheet"
#~ "the hole, not its center.<br><br>This can also be thought of as the "
#~ "\"drilling tolerance\" as it only includes **round** holes (see "
#~ "`edge_clearance` for the milling tolerance)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `silk_clearance` | min/opt/"
#~ "max "
#~ "| Checks the clearance between objects on silkscreen layers and other "
#~ "objects."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `skew` | "
#~ "max "
@ -37618,52 +37575,71 @@ msgstr "KiCad Drawing Sheet"
#~ "the lengths of each net that is matched by the rule. If the absolute "
#~ "value of the difference between that average and the length of any one "
#~ "net is above the constraint `max` value, an error will be generated."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `solder_mask_expansion` | "
#~ "opt "
#~ "| Specifies the solder mask expansion for pads, shapes and "
#~ "tracks. "
#~ "|\n"
#~ "| `solder_paste_abs_margin` | "
#~ "opt "
#~ "| Specifies the absolute solder paste clearance for pads. Usually "
#~ "negative to inset the paste.<br><br>The final solder paste clearace will "
#~ "be the absolute clearance plus the relative "
#~ "clearance. "
#~ "|\n"
#~ "| `solder_paste_rel_margin` | "
#~ "opt "
#~ "| Specifies the relative solder paste clearance for pads. Usually "
#~ "negative to inset the paste.<br><br>The final solder paste clearace will "
#~ "be the absolute clearance plus the relative "
#~ "clearance. "
#~ "|\n"
#~ "| `thermal_relief_gap` | "
#~ "min "
#~ "| Specifies the width of the gap between a pad and a zone with a thermal-"
#~ "relief connection."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `thermal_spoke_width` | "
#~ "opt "
#~ "| Specifies the width of the spokes connecting a pad to a zone with a "
#~ "thermal-relief connection."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_width` | min/opt/"
#~ "max "
#~ "| Checks the width of track and arc segments. An error will be generated "
#~ "for each segment that has a width below the `min` value (if specified) or "
#~ "above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_angle` | min/opt/"
#~ "max "
#~ "| Checks the angle between two connected track segments. An error will "
#~ "be generated for each connected pair with an angle below the `min` value "
#~ "(if specified) or above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `track_segment_length` | min/"
#~ "max "
#~ "| Checks the length of track and arc segments. An error will be "
#~ "generated for each segment that has a length below the `min` value (if "
#~ "specified) or above the `max` value (if specified)."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `via_count` | "
#~ "max "
#~ "| Counts the number of vias on every net matched by the rule condition. "
#~ "If that number exceeds the constraint `max` value on any matched net, an "
#~ "error will be generated for that net."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "| `zone_connection` | "
#~ "`solid`<br>`thermal_reliefs`<br>`none` "
#~ "| Specifies the connection to be made between a zone and a pad."
#~ "<br> "
#~ "<br> "
#~ "|\n"
#~ "\n"
#~ "\n"
@ -37812,6 +37788,18 @@ msgstr "KiCad Drawing Sheet"
#~ " (constraint hole_to_hole)\n"
#~ " (severity ignore))\n"
#~ "\n"
#~ "\n"
#~ " # No solder mask expansion for vias.\n"
#~ " (rule \"no mask expansion on vias\"\n"
#~ " (constraint solder_mask_expansion (opt 0mm))\n"
#~ " (condition \"A.type == via\"))\n"
#~ "\n"
#~ "\n"
#~ " # Remove solder paste from DNP footprints.\n"
#~ " (rule remove_solder_paste_from_DNP\n"
#~ " (constraint solder_paste_abs_margin (opt -50mm))\n"
#~ " (condition \"A.Do_not_Populate\"))\n"
#~ "\n"
#~ msgstr ""
#~ "### More Examples\n"
#~ "\n"
@ -37956,6 +37944,18 @@ msgstr "KiCad Drawing Sheet"
#~ " (constraint hole_to_hole)\n"
#~ " (severity ignore))\n"
#~ "\n"
#~ "\n"
#~ " # No solder mask expansion for vias.\n"
#~ " (rule \"no mask expansion on vias\"\n"
#~ " (constraint solder_mask_expansion (opt 0mm))\n"
#~ " (condition \"A.type == via\"))\n"
#~ "\n"
#~ "\n"
#~ " # Remove solder paste from DNP footprints.\n"
#~ " (rule remove_solder_paste_from_DNP\n"
#~ " (constraint solder_paste_abs_margin (opt -50mm))\n"
#~ " (condition \"A.Do_not_Populate\"))\n"
#~ "\n"
#, c-format
#~ msgid ""

95
translation/pofiles/es.po
View File

@ -20,7 +20,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad Spanish Translation\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-04-04 12:49+0000\n"
"Last-Translator: Adolfo Jayme Barrientos <fitojb@ubuntu.com>\n"
"Language-Team: Spanish <https://hosted.weblate.org/projects/kicad/v9/es/>\n"
@ -12571,7 +12571,7 @@ msgstr ""
"hoja."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13033,7 +13033,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propiedades de la etiqueta jerárquica"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propiedades de la etiqueta"
@ -13045,23 +13045,23 @@ msgstr "Propiedades de la etiqueta directiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propiedades de pin de hoja jerárquica"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "La etiqueta no puede estar vacía."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "sin título"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Editar propiedades de la etiqueta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "El primer campo es obligatorio."
@ -40660,18 +40660,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40680,7 +40680,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40688,12 +40688,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40701,7 +40701,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40709,7 +40709,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40718,21 +40718,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40740,14 +40740,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40762,7 +40762,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40771,13 +40771,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40786,71 +40786,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41674,18 +41655,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/es_MX.po
View File

@ -17,7 +17,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad Spanish Translation\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-03-25 19:16+0000\n"
"Last-Translator: lylythechosenone <Lysander.mealy@gmail.com>\n"
"Language-Team: Spanish (Mexico) <https://hosted.weblate.org/projects/kicad/"
@ -12663,7 +12663,7 @@ msgstr ""
"las Propiedades de la hoja."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13124,7 +13124,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propiedades de la etiqueta jerárquica"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propiedades de la etiqueta"
@ -13136,22 +13136,22 @@ msgstr "Propiedades de la etiqueta directiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propiedades de pin de hoja jerárquica"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "La etiqueta no puede estar vacía."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "sin título"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Editar propiedades de la etiqueta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "El primer campo es obligatorio."
@ -40834,18 +40834,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40854,7 +40854,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40862,12 +40862,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40875,7 +40875,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40883,7 +40883,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40892,21 +40892,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40914,14 +40914,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40936,7 +40936,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40945,13 +40945,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40960,71 +40960,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41876,18 +41857,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/et.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-04-25 23:42+0000\n"
"Last-Translator: Ivan Chuba <xtrvweb@gmail.com>\n"
"Language-Team: Estonian <https://hosted.weblate.org/projects/kicad/v9/et/>\n"
@ -11940,7 +11940,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12387,7 +12387,7 @@ msgid "Hierarchical Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr ""
@ -12399,22 +12399,22 @@ msgstr ""
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -37907,18 +37907,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -37927,7 +37927,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -37935,12 +37935,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -37948,7 +37948,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -37956,7 +37956,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -37965,21 +37965,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -37987,14 +37987,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -38009,7 +38009,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -38018,13 +38018,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -38033,71 +38033,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -38464,18 +38445,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/fi.po
View File

@ -19,7 +19,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-05-01 03:03+0000\n"
"Last-Translator: Toni Laiho <apelegeos@gmail.com>\n"
"Language-Team: Finnish <https://hosted.weblate.org/projects/kicad/v9/fi/>\n"
@ -12411,7 +12411,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Lehden tiedostonimeä voi muokata vain Lehden ominaisuudet -dialogista."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12866,7 +12866,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hierarkisen nimiön ominaisuudet"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Nimiön ominaisuudet"
@ -12878,22 +12878,22 @@ msgstr "Ohjaavan Nimikkeen Ominaisuudet"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarkkisen lehden nastan ominaisuudet"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Etiketti ei voi olla tyhjä."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "nimetön"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Muokkaa nimiön ominaisuuksia"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Ensimmäinen kenttä on pakollinen."
@ -39906,18 +39906,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39926,7 +39926,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39934,12 +39934,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39947,7 +39947,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39955,7 +39955,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39964,21 +39964,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39986,14 +39986,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40008,7 +40008,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40017,13 +40017,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40032,71 +40032,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40487,18 +40468,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/fr.po
View File

@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-04-22 10:24+0200\n"
"Last-Translator: \n"
"Language-Team: jp-charras\n"
@ -12463,7 +12463,7 @@ msgstr ""
"propriétés de feuille."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12921,7 +12921,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propriétés de Label Hiérarchique"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propriétés du label"
@ -12933,22 +12933,22 @@ msgstr "Propriétés de Label de Directive"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propriétés du Label Hiérarchique"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Le label ne peut pas être vide."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "untitled"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Editer Propriétés du Label"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Le premier champ est obligatoire."
@ -40312,18 +40312,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40332,7 +40332,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40340,12 +40340,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40353,7 +40353,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40361,7 +40361,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40370,21 +40370,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40392,14 +40392,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40414,7 +40414,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40423,13 +40423,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40438,71 +40438,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41244,18 +41225,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### More Examples\n"
"\n"

95
translation/pofiles/he.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2024-11-26 08:01+0000\n"
"Last-Translator: \"G.B\" <glbarak@gmail.com>\n"
"Language-Team: Hebrew <https://hosted.weblate.org/projects/kicad/master-"
@ -12040,7 +12040,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12486,7 +12486,7 @@ msgid "Hierarchical Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr ""
@ -12498,22 +12498,22 @@ msgstr ""
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -38072,18 +38072,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -38092,7 +38092,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -38100,12 +38100,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -38113,7 +38113,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -38121,7 +38121,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -38130,21 +38130,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -38152,14 +38152,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -38174,7 +38174,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -38183,13 +38183,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -38198,71 +38198,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -38629,18 +38610,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/hr.po
View File

@ -2,7 +2,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2024-12-10 16:04-0800\n"
"Language: hr\n"
"MIME-Version: 1.0\n"
@ -11866,7 +11866,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12312,7 +12312,7 @@ msgid "Hierarchical Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr ""
@ -12324,22 +12324,22 @@ msgstr ""
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -37724,18 +37724,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -37744,7 +37744,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -37752,12 +37752,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -37765,7 +37765,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -37773,7 +37773,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -37782,21 +37782,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -37804,14 +37804,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -37826,7 +37826,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -37835,13 +37835,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -37850,71 +37850,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -38281,18 +38262,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/hu.po
View File

@ -12,7 +12,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-07 14:41+0000\n"
"Last-Translator: Sárkány Lőrinc <lsarkany@gmail.com>\n"
"Language-Team: Hungarian <https://hosted.weblate.org/projects/kicad/v9/hu/>\n"
@ -12871,7 +12871,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Elem tulajdonságok párbeszédablak megnyitása"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13360,7 +13360,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hierarchikus címke tulajdonságok"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Címke tulajdonságok"
@ -13374,22 +13374,22 @@ msgstr "Hierarchikus címke tulajdonságok"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarchikus lap kivezető láb tulajdonságai"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Címke nem lehet üres."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "névtelen"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Címke tulajdonságok"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Az első mező nem lehet üres."
@ -42353,18 +42353,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -42373,7 +42373,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -42381,12 +42381,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -42394,7 +42394,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -42402,7 +42402,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -42411,21 +42411,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -42433,14 +42433,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -42455,7 +42455,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -42464,13 +42464,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -42479,71 +42479,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42910,18 +42891,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/id.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2022-12-17 19:13+0000\n"
"Last-Translator: Neko Nekowazarashi <kodra@nekoweb.my.id>\n"
"Language-Team: Indonesian <https://hosted.weblate.org/projects/kicad/master-"
@ -12965,7 +12965,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13472,7 +13472,7 @@ msgid "Hierarchical Label Properties"
msgstr "Label Hirarkis"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
#, fuzzy
msgid "Label Properties"
msgstr "Properti Teks"
@ -13487,24 +13487,24 @@ msgstr "Properti Elektrikal"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Properti Segmen Garis"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Nama berkas footprint \"%s\" tidak valid."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "tak berjudul"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Properti Teks"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -41675,18 +41675,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41695,7 +41695,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41703,12 +41703,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41716,7 +41716,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41724,7 +41724,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41733,21 +41733,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41755,14 +41755,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41777,7 +41777,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41786,13 +41786,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41801,71 +41801,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42232,18 +42213,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/it.po
View File

@ -115,7 +115,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-27 06:01+0000\n"
"Last-Translator: Marco Ciampa <ciampix@posteo.net>\n"
"Language-Team: Italian <https://hosted.weblate.org/projects/kicad/v9/it/>\n"
@ -12487,7 +12487,7 @@ msgstr ""
"del foglio."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12942,7 +12942,7 @@ msgid "Hierarchical Label Properties"
msgstr "Proprietà etichetta gerarchica"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Proprietà etichetta"
@ -12954,22 +12954,22 @@ msgstr "Proprietà etichetta direttiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Proprietà piedino foglio gerarchico"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "L'etichetta non può essere vuota."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "senza-titolo"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Modifica proprietà etichetta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Il primo campo è obbligatorio."
@ -40096,18 +40096,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40116,7 +40116,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40124,12 +40124,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40137,7 +40137,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40145,7 +40145,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40154,21 +40154,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40176,14 +40176,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40198,7 +40198,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40207,13 +40207,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40222,71 +40222,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41295,18 +41276,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Ulteriori esempi\n"
"\n"

122
translation/pofiles/ja.po
View File

@ -15,7 +15,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-05 22:37+0000\n"
"Last-Translator: co8 j <co8@nifty.com>\n"
"Language-Team: Japanese <https://hosted.weblate.org/projects/kicad/v9/ja/>\n"
@ -12309,7 +12309,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "シートのファイル名はシートのプロパティダイアログでのみ変更できます。"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12764,7 +12764,7 @@ msgid "Hierarchical Label Properties"
msgstr "階層ラベルのプロパティ"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "ラベルのプロパティ"
@ -12776,22 +12776,22 @@ msgstr "指示ラベルのプロパティ"
msgid "Hierarchical Sheet Pin Properties"
msgstr "階層シートピンのプロパティ"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "ラベルは空にできません。"
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "名称未設定"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "ラベルのプロパティを編集"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "最初のフィールドは必須です。"
@ -39667,24 +39667,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39693,7 +39694,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39701,12 +39702,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39714,7 +39715,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39722,7 +39723,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39731,21 +39732,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39753,14 +39754,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39775,7 +39776,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39784,13 +39785,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39799,71 +39800,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40480,6 +40462,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -40623,18 +40606,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### さらなる例\n"
"\n"
@ -40657,13 +40628,13 @@ msgstr ""
"\n"
" (rule \"Distance between Vias of Different Nets\"\n"
" (constraint hole_to_hole (min 0.254mm))\n"
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))"
"\n"
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B."
"Net\"))\n"
"\n"
" (rule \"Clearance between Pads of Different Nets\"\n"
" (constraint clearance (min 3.0mm))\n"
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))"
"\n"
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B."
"Net\"))\n"
"\n"
"\n"
" (rule \"Via Hole to Track Clearance\"\n"
@ -40714,9 +40685,8 @@ msgstr ""
" (constraint thermal_relief_gap (min 10mil))\n"
" (constraint thermal_spoke_width (min 12mil)))\n"
"\n"
" # "
"GNDとPWRのゾーンに対してサーマルリリーフギャップとスポーク幅をオーバライドす"
"る\n"
" # GNDとPWRのゾーンに対してサーマルリリーフギャップとスポーク幅をオーバラ"
"イドする\n"
" (rule defined_relief_pwr\n"
" (constraint thermal_relief_gap (min 10mil))\n"
" (constraint thermal_spoke_width (min 12mil))\n"
@ -40775,8 +40745,8 @@ msgstr ""
"drilling \n"
" # micro-vias.\n"
" (rule hole_to_hole_uvia_exclusion\n"
" (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'\")"
"\n"
" (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == "
"'Micro'\")\n"
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
@ -42651,8 +42621,9 @@ msgstr "セグメントの端を追加できませんでした (%d %d) -> (%d %d
msgid ""
"Failed to add arc curve from (%d %d), arc p0 (%d %d), mid (%d %d), p1 (%d "
"%d)\n"
msgstr "円弧の曲線を (%d %d) から追加するのに失敗、円弧 p0 (%d %d)、mid (%d %d)、p1 ("
"%d %d)\n"
msgstr ""
"円弧の曲線を (%d %d) から追加するのに失敗、円弧 p0 (%d %d)、mid (%d %d)、p1 "
"(%d %d)\n"
#: pcbnew/exporters/step/step_pcb_model.cpp:1570
#, c-format
@ -42734,7 +42705,8 @@ msgstr "ビア"
#: pcbnew/exporters/step/step_pcb_model.cpp:3245
#, c-format
msgid "No valid PCB assembly; cannot create output file '%s'.\n"
msgstr "有効な基板アセンブリがありません。出力ファイル '%s' を作成できません。\n"
msgstr ""
"有効な基板アセンブリがありません。出力ファイル '%s' を作成できません。\n"
#: pcbnew/exporters/step/step_pcb_model.cpp:2322
msgid "Failed to set STEP product name, but will attempt to continue."

95
translation/pofiles/ka.po
View File

@ -3,7 +3,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-29 02:37+0000\n"
"Last-Translator: Temuri Doghonadze <temuri.doghonadze@gmail.com>\n"
"Language-Team: Georgian <https://hosted.weblate.org/projects/kicad/v9/ka/>\n"
@ -12067,7 +12067,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12515,7 +12515,7 @@ msgid "Hierarchical Label Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "ჭდის თვისებები"
@ -12527,23 +12527,23 @@ msgstr ""
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "უსახელო"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "ჭდის თვისებები"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -38316,18 +38316,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -38336,7 +38336,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -38344,12 +38344,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -38357,7 +38357,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -38365,7 +38365,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -38374,21 +38374,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -38396,14 +38396,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -38418,7 +38418,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -38427,13 +38427,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -38442,71 +38442,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -38873,18 +38854,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/ko.po
View File

@ -35,7 +35,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-05 14:56+0000\n"
"Last-Translator: 김랑기 <korearf@gmail.com>\n"
"Language-Team: Korean <https://hosted.weblate.org/projects/kicad/v9/ko/>\n"
@ -12261,7 +12261,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "시트 파일명은 시트 설정 대화 상자에서만 변경할 수 있습니다."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12713,7 +12713,7 @@ msgid "Hierarchical Label Properties"
msgstr "계층 라벨 속성"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "라벨 속성"
@ -12725,22 +12725,22 @@ msgstr "지시문 레이블 속성"
msgid "Hierarchical Sheet Pin Properties"
msgstr "계층 시트 핀 속성"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "레이블은 비워둘 수 없습니다."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "제목 없음"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "라벨 속성 편집"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "첫 번째 필드는 필수입니다."
@ -39474,18 +39474,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39494,7 +39494,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39502,12 +39502,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39515,7 +39515,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39523,7 +39523,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39532,21 +39532,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39554,14 +39554,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39576,7 +39576,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39585,13 +39585,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39600,71 +39600,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40393,18 +40374,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### 추가 예제\n"
"\n"

95
translation/pofiles/lt.po
View File

@ -9,7 +9,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad 4.0\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-01-23 15:38+0000\n"
"Last-Translator: John Beard <john.j.beard@gmail.com>\n"
"Language-Team: Lithuanian <https://hosted.weblate.org/projects/kicad/master-"
@ -12962,7 +12962,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Rodomas elemento ypatybių dialogo langas"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -13445,7 +13445,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hierarchinės žymos savybės"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Žymos savybės"
@ -13458,12 +13458,12 @@ msgstr "Hierarchinės žymos savybės"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarchinės lapo kaiščių savybės"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Grynasis vardas negali būti tuščias."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13471,12 +13471,12 @@ msgstr "Grynasis vardas negali būti tuščias."
msgid "untitled"
msgstr "Kiekis"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Žymos savybės"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "Pirmieji %d laukai yra privalomi."
@ -41966,18 +41966,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41986,7 +41986,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41994,12 +41994,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -42007,7 +42007,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -42015,7 +42015,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -42024,21 +42024,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -42046,14 +42046,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -42068,7 +42068,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -42077,13 +42077,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -42092,71 +42092,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42523,18 +42504,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/lv.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad 6.0\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-19 12:01+0000\n"
"Last-Translator: \"ℂ𝕠𝕠𝕠𝕝 (𝕘𝕚𝕥𝕙𝕦𝕓.𝕔𝕠𝕞/ℂ𝕠𝕠𝕠𝕝)\" <coool@mail.lv>\n"
"Language-Team: Latvian <https://hosted.weblate.org/projects/kicad/v9/lv/>\n"
@ -12671,7 +12671,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13151,7 +13151,7 @@ msgid "Hierarchical Label Properties"
msgstr "Izveidot slāņus"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
#, fuzzy
msgid "Label Properties"
msgstr "Materiālu īpašības"
@ -13165,23 +13165,23 @@ msgstr "Materiālu īpašības"
msgid "Hierarchical Sheet Pin Properties"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Materiālu īpašības"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -40150,18 +40150,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40170,7 +40170,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40178,12 +40178,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40191,7 +40191,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40199,7 +40199,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40208,21 +40208,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40230,14 +40230,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40252,7 +40252,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40261,13 +40261,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40276,71 +40276,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40707,18 +40688,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/nl.po
View File

@ -17,7 +17,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-02-19 03:14+0000\n"
"Last-Translator: Seth Hillbrand <seth@kipro-pcb.com>\n"
"Language-Team: Dutch <https://hosted.weblate.org/projects/kicad/master-"
@ -12576,7 +12576,7 @@ msgstr ""
"Bladbestandsnaam kan alleen gewijzigd worden in het bladeigenschappenscherm."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13034,7 +13034,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hiërarchische labeleigenschappen"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Labeleigenschappen"
@ -13046,22 +13046,22 @@ msgstr "Eigenschappen richtlijnlabels"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hiërarchische bladpin-eigenschappen"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Label mag niet leeg zijn."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "naamloos"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Labeleigenschappen bewerken"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Het eerste veld is verplicht."
@ -40458,18 +40458,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40478,7 +40478,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40486,12 +40486,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40499,7 +40499,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40507,7 +40507,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40516,21 +40516,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40538,14 +40538,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40560,7 +40560,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40569,13 +40569,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40584,71 +40584,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41478,18 +41459,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/no.po
View File

@ -9,7 +9,7 @@ msgid ""
msgstr ""
"Project-Id-Version: 5.99\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-04-30 19:05+0000\n"
"Last-Translator: Stian Kristensen <stiank@gmail.com>\n"
"Language-Team: Norwegian Bokmål <https://hosted.weblate.org/projects/kicad/"
@ -12819,7 +12819,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Viser dialogboksen for elementegenskaper"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -13306,7 +13306,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hierarkiske etikettegenskaper"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Merkegenskaper"
@ -13319,12 +13319,12 @@ msgstr "Hierarkiske etikettegenskaper"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarkiske arkpinnegenskaper"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Nettnavnet kan ikke være tomt."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13332,12 +13332,12 @@ msgstr "Nettnavnet kan ikke være tomt."
msgid "untitled"
msgstr "Untitled Sheet"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Merkegenskaper"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "De første %d feltene er obligatoriske."
@ -41770,18 +41770,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41790,7 +41790,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41798,12 +41798,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41811,7 +41811,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41819,7 +41819,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41828,21 +41828,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41850,14 +41850,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41872,7 +41872,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41881,13 +41881,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41896,71 +41896,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42327,18 +42308,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

97
translation/pofiles/pl.po
View File

@ -17,7 +17,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-28 07:04+0000\n"
"Last-Translator: ZbeeGin <zbeegin@op.pl>\n"
"Language-Team: Polish <https://hosted.weblate.org/projects/kicad/v9/pl/>\n"
@ -12391,7 +12391,7 @@ msgstr ""
"arkusza."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12847,7 +12847,7 @@ msgid "Hierarchical Label Properties"
msgstr "Właściwości etykiety hierarchicznej"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Właściwości etykiety"
@ -12859,22 +12859,22 @@ msgstr "Właściwości etykiety z dyrektywą"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Właściwości pinów arkusza hierarchicznego"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Nazwa etykiety nie może być pusta."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "bez_nazwy"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Edycja właściwości etykiety"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Pierwsze pole jest obowiązkowe."
@ -40025,24 +40025,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40051,7 +40052,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40059,12 +40060,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40072,7 +40073,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40080,7 +40081,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40089,21 +40090,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40111,14 +40112,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40133,7 +40134,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40142,13 +40143,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40157,71 +40158,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40852,6 +40834,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -40995,18 +40978,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Więcej przykładów\n"
"\n"

99
translation/pofiles/pt.po
View File

@ -14,11 +14,11 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-04 18:01+0000\n"
"Last-Translator: dsa-t <dudesuchamazing@gmail.com>\n"
"Language-Team: Portuguese <https://hosted.weblate.org/projects/kicad/v9/pt/>"
"\n"
"Language-Team: Portuguese <https://hosted.weblate.org/projects/kicad/v9/pt/"
">\n"
"Language: pt\n"
"MIME-Version: 1.0\n"
"Content-Type: text/plain; charset=UTF-8\n"
@ -12568,7 +12568,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "O nome da página só pode ser modificado nas propriedades da página."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13025,7 +13025,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propriedades de Rótulo Hierárquico"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propriedades do Rótulo"
@ -13037,22 +13037,22 @@ msgstr "Propriedades da etiqueta diretiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propriedades do Pino de Folha Hierárquicas"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "A etiqueta não pode estar vazia."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "sem título"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Editar as propriedades da etiqueta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "O primeiro campo é obrigatório."
@ -40466,18 +40466,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40486,7 +40486,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40494,12 +40494,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40507,7 +40507,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40515,7 +40515,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40524,21 +40524,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40546,14 +40546,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40568,7 +40568,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40577,13 +40577,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40592,71 +40592,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41023,18 +41004,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/pt_BR.po
View File

@ -15,7 +15,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-03-27 13:55+0000\n"
"Last-Translator: Wellington Terumi Uemura <wellingtonuemura@gmail.com>\n"
"Language-Team: Portuguese (Brazil) <https://hosted.weblate.org/projects/"
@ -12482,7 +12482,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "O nome da página só pode ser modificado nas propriedades da página."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12939,7 +12939,7 @@ msgid "Hierarchical Label Properties"
msgstr "Propriedades do rótulo hierárquico"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Propriedades do rótulo"
@ -12951,22 +12951,22 @@ msgstr "Propriedades da etiqueta diretiva"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Propriedades do pino da folha hierárquicas"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "A etiqueta não pode estar vazia."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "sem título"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Editar as propriedades da etiqueta"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "O primeiro campo é obrigatório."
@ -40225,18 +40225,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40245,7 +40245,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40253,12 +40253,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40266,7 +40266,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40274,7 +40274,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40283,21 +40283,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40305,14 +40305,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40327,7 +40327,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40336,13 +40336,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40351,71 +40351,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41151,18 +41132,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### More Examples\n"
"\n"

95
translation/pofiles/ro.po
View File

@ -7,7 +7,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-20 20:01+0000\n"
"Last-Translator: Peter B <sleepyghostshark@users.noreply.hosted.weblate."
"org>\n"
@ -12840,7 +12840,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr ""
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -13347,7 +13347,7 @@ msgid "Hierarchical Label Properties"
msgstr "Proprietăți ale etichetelor ierarhice"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Proprietățile etichetei"
@ -13361,12 +13361,12 @@ msgstr "Proprietăți ale etichetelor ierarhice"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Proprietăți ale etichetelor ierarhice"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Valoarea nu poate fi goală."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13374,12 +13374,12 @@ msgstr "Valoarea nu poate fi goală."
msgid "untitled"
msgstr "Cantitate"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Proprietățile etichetei"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr ""
@ -41733,18 +41733,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41753,7 +41753,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41761,12 +41761,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41774,7 +41774,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41782,7 +41782,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41791,21 +41791,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41813,14 +41813,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41835,7 +41835,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41844,13 +41844,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41859,71 +41859,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42290,18 +42271,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

242
translation/pofiles/ru.po
View File

@ -21,7 +21,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-07 14:41+0000\n"
"Last-Translator: dsa-t <dudesuchamazing@gmail.com>\n"
"Language-Team: Russian <https://hosted.weblate.org/projects/kicad/v9/ru/>\n"
@ -12364,7 +12364,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Имя файла листа можно изменить только в диалоге свойств листа."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12819,7 +12819,7 @@ msgid "Hierarchical Label Properties"
msgstr "Свойства иерархической метки"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Свойства метки"
@ -12831,22 +12831,22 @@ msgstr "Свойства директивной метки"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Свойства вывода иерархического листа"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Имя метки не может быть пустой."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "без имени"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Править свойства метки"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Первое поле - обязательное."
@ -39868,24 +39868,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39894,7 +39895,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39902,12 +39903,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39915,7 +39916,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39923,7 +39924,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39932,21 +39933,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39954,14 +39955,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39976,7 +39977,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39985,13 +39986,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40000,71 +40001,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40076,101 +40058,100 @@ msgstr ""
"| "
"Описание "
"|\n"
"|---------------------------|------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|"
"\n"
"|---------------------------|------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Проверяет ширину поясков "
"перех.отв.<br> "
"| Проверяет ширину поясков перех.отв."
"<br> "
"|\n"
"| `assertion` | \"&lt;expression>\""
" "
"| Проверяет заданное "
"выражение.<br> "
"| `assertion` | \"&lt;"
"expression>\" "
"| Проверяет заданное выражение."
"<br> "
"|\n"
"| `clearance` | "
"min "
"| Определяет **электрический** зазор между медными объектами разных цепей. ("
"См. `physical_clearance`, если хотите указать зазор между объектами "
"| Определяет **электрический** зазор между медными объектами разных цепей. "
"(См. `physical_clearance`, если хотите указать зазор между объектами "
"независимо от цепи.)<br><br> Чтобы разрешить медным объектам пересекаться "
"(сталкиваться), создайте ограничение `clearance` со значением `min` меньше "
"нуля (например, `-1`)"
".<br> "
"нуля (например, `-1`)."
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
"| Проверяет расстояние между областями установки посад.мест и генерирует "
"ошибку, если любые две области находятся ближе, чем `min` расстояние. Если "
"посад.место не имеет области установки, это ограничение не создает "
"ошибок.<br> "
"посад.место не имеет области установки, это ограничение не создает ошибок."
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Определяет длину пути утечки между медными объектами разных "
"цепей.<br> "
"| Определяет длину пути утечки между медными объектами разных цепей."
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
"| Проверяет зазор между связанными дорожками в дифференциальной паре. "
"Связанные дорожки - это сегменты, параллельные друг другу. Зазор между "
"дифференциальными парами не проверяется на несвязанных участках "
"дифференциальной пары (например, на выходе из компонента)"
".<br> "
"дифференциальной пары (например, на выходе из компонента)."
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
"| Проверяет расстояние, на которое дорожка дифференциальной пары проходит "
"без связи с дорожкой другой полярности в паре (например, когда пара выходит "
"из компонента или становится без связи, чтобы обойти другой объект, "
"например, перех.отв.)"
".<br> "
"например, перех.отв.)."
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`"
"<br> | Укажите один или несколько типов объектов для запрета, разделенных "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
"| Укажите один или несколько типов объектов для запрета, разделенных "
"пробелами. Например, `(constraint disallow track)` или `(constraint "
"disallow track via pad)`. Если объект этого типа соответствует условию "
"правила, будет создана ошибка DRC.<br><br>Это ограничение, по сути, "
"аналогично области правил запрета, но может быть использовано для создания "
"более конкретных ограничений "
"запрета.<br> "
"|\n"
"более конкретных ограничений запрета."
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Проверяет зазор между объектами и краем платы.<br><br>Это также можно "
"считать \"допуском на фрезеровку\", поскольку край платы будет включать все "
"графические элементы на слое `Edge.Cuts`, а также любые *овальные* отверстия "
"в конт.пл. (См. `physical_hole_clearance` для допуска на сверление)"
"<br> "
"в конт.пл. (См. `physical_hole_clearance` для допуска на "
"сверление)<br> "
"|\n"
"| `length` | min/"
"max "
"| Проверяет общую проложенную длину для цепей, соответствующих условию "
"правила, и выдает ошибку для каждой цепи, длина которой меньше значения `min`"
" (если указано) или больше значения `max` (если указано), заданного "
"ограничением.<br> "
"правила, и выдает ошибку для каждой цепи, длина которой меньше значения "
"`min` (если указано) или больше значения `max` (если указано), заданного "
"ограничением."
"<br> "
"|\n"
"| `hole` | min/"
"max "
"| Проверяет размер (диаметр) сверленного отверстия в конт.пл. или "
"перех.отв. Для овальных отверстий меньший (минорный) диаметр проверяется "
"| Проверяет размер (диаметр) сверленного отверстия в конт.пл. или перех."
"отв. Для овальных отверстий меньший (минорный) диаметр проверяется "
"относительно значения `min` (если указано), а больший (основной) диаметр "
"проверяется относительно значения `max` (если указано)"
".<br> "
"проверяется относительно значения `max` (если указано)."
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Проверяет зазор между просверленным отверстием в конт.пл. или перех.отв. и "
"медными объектами другой цепи. Зазор измеряется от диаметра отверстия, а не "
"от "
"центра.<br> "
"от центра."
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
"| Проверяет зазор между механически сверленными отверстиями в конт.пл. и "
"перех.отв. Зазор измеряется между диаметрами отверстий, а не между "
"центрами.<br><br>Это ограничение служит только для защиты сверл. Зазор "
"между **просверленными лазером** (микроотверстиями) и другими отверстиями, "
"перех.отв. Зазор измеряется между диаметрами отверстий, а не между центрами."
"<br><br>Это ограничение служит только для защиты сверл. Зазор между "
"**просверленными лазером** (микроотверстиями) и другими отверстиями, "
"просверленными не механически, не проверяется, также как и зазор между "
"**фрезерованными** (овальной формы) и другими отверстиями, сделанными не "
"механически.<br> |\n"
@ -40178,22 +40159,22 @@ msgstr ""
"min "
"| Проверяет зазор между двумя объектами на заданном слое (включая немедные "
"слои).<br><br>Хотя эта функция может выполнять более широкие проверки, чем "
"`clearance`, она намного медленнее. По возможности используйте `clearance`"
".<br> "
"`clearance`, она намного медленнее. По возможности используйте `clearance`."
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
"| Проверяет зазор между сверленным отверстием в конт.пл. или перех.отв. и "
"другим объектом, независимо от цепи. Зазор измеряется от диаметра отверстия, "
"а не от центра.<br><br>Это также можно рассматривать как \"допуск сверления\""
", поскольку он учитывает только **круглые** отверстия (см. `edge_clearance` "
"для допуска фрезеровки)"
".<br> "
"а не от центра.<br><br>Это также можно рассматривать как \"допуск "
"сверления\", поскольку он учитывает только **круглые** отверстия (см. "
"`edge_clearance` для допуска фрезеровки)."
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Проверяет зазор между объектами на слоях шелкографии и другими "
"объектами.<br> "
"| Проверяет зазор между объектами на слоях шелкографии и другими объектами."
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40201,8 +40182,8 @@ msgstr ""
"есть разницу между длиной каждой цепи и средним значением всех длин цепей, "
"соответствующих правилу. Если абсолютное значение разницы между средним "
"значением и длиной какой-либо цепи превышает значение ограничения `max`, "
"будет сгенерирована "
"ошибка.<br> "
"будет сгенерирована ошибка."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
@ -40225,46 +40206,46 @@ msgstr ""
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Задает зазор терморазгрузки в соединении конт.пл. с "
"зоной.<br> "
"| Задает зазор терморазгрузки в соединении конт.пл. с зоной."
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Задает ширину мостиков терморазгрузки в соединении конт.пл. с "
"зоной.<br> "
"| Задает ширину мостиков терморазгрузки в соединении конт.пл. с зоной."
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Проверяет ширину сегментов дорожек и дуг. Для каждого сегмента, ширина "
"которого меньше `min` (если указано) или больше `max` (если указано), будет "
"выдана "
"ошибка.<br> "
"выдана ошибка."
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Проверяет угол между двумя соединенными сегментами дорожки. Для каждой "
"пары соединенных сегментов с углом ниже значения `min` (если указано) или "
"выше значения `max` (если указано) будет сгенерирована "
"ошибка.<br> "
"выше значения `max` (если указано) будет сгенерирована ошибка."
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Проверяет длину сегментов дорожек и дуг. Для каждого сегмента, длина "
"которого меньше `min` (если указано) или больше `max` (если указано), будет "
"выдана "
"ошибка.<br> "
"выдана ошибка."
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Считает количество перех.отв. в каждой цеп и, соответствующей условию "
"правила. Если это число превышает значение `max` в любой совпадающей цепи, "
"для этой цепи будет сгенерирована "
"ошибка.<br> "
"для этой цепи будет сгенерирована ошибка."
"<br> "
"|\n"
"| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none`"
" "
"| Задает соединение, выполняемое между зоной и конт. "
"площадкой.<br> "
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Задает соединение, выполняемое между зоной и конт. площадкой."
"<br> "
"|\n"
"\n"
"\n"
@ -40672,6 +40653,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -40815,18 +40797,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Ещё примеры\n"
"\n"
@ -40849,13 +40819,13 @@ msgstr ""
"\n"
" (rule \"Distance between Vias of Different Nets\"\n"
" (constraint hole_to_hole (min 0.254mm))\n"
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))"
"\n"
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B."
"Net\"))\n"
"\n"
" (rule \"Clearance between Pads of Different Nets\"\n"
" (constraint clearance (min 3.0mm))\n"
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))"
"\n"
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B."
"Net\"))\n"
"\n"
"\n"
" (rule \"Via Hole to Track Clearance\"\n"
@ -40892,8 +40862,8 @@ msgstr ""
" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
"\n"
"\n"
" # Не использовать терморазгрузку на конт.пл. с параметром "
"\"для отвода тепла\"\n"
" # Не использовать терморазгрузку на конт.пл. с параметром \"для отвода "
"тепла\"\n"
" (rule heat_sink_pad\n"
" (constraint zone_connection solid)\n"
" (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
@ -40969,8 +40939,8 @@ msgstr ""
" # глухих/внутренних перех. отв. перед лазерным сверлением перех. "
"микроотв.\n"
" (rule hole_to_hole_uvia_exclusion\n"
" (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == 'Micro'\")"
"\n"
" (condition \"A.Via_Type == 'Blind/buried' && B.Via_Type == "
"'Micro'\")\n"
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"

95
translation/pofiles/sk.po
View File

@ -11,7 +11,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-05-26 23:01+0000\n"
"Last-Translator: EdizonTN <EdizonTN@users.noreply.hosted.weblate.org>\n"
"Language-Team: Slovak <https://hosted.weblate.org/projects/kicad/v9/sk/>\n"
@ -12635,7 +12635,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Zobraziť vlastnosti položky"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13116,7 +13116,7 @@ msgid "Hierarchical Label Properties"
msgstr "Vlastnosti hierarchickej menovky"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Vlastnosti menovky"
@ -13129,12 +13129,12 @@ msgstr "Vlastnosti hierarchickej menovky"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hierarchické vlastnosti čapu listu"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Názov siete nemôže byť prázdny."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13142,11 +13142,11 @@ msgstr "Názov siete nemôže byť prázdny."
msgid "untitled"
msgstr "Počet"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Upraviť vlastnosti menovky"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "Prvých %d polí je povinných."
@ -41522,18 +41522,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41542,7 +41542,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41550,12 +41550,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41563,7 +41563,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41571,7 +41571,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41580,21 +41580,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41602,14 +41602,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41624,7 +41624,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41633,13 +41633,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41648,71 +41648,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42079,18 +42060,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/sl.po
View File

@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-01-23 15:38+0000\n"
"Last-Translator: John Beard <john.j.beard@gmail.com>\n"
"Language-Team: Slovenian <https://hosted.weblate.org/projects/kicad/master-"
@ -13952,7 +13952,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Prikaže pogovorno okno z lastnostmi elementov"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -14474,7 +14474,7 @@ msgid "Hierarchical Label Properties"
msgstr "Lastnosti hierarhična oznaka"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
#, fuzzy
msgid "Label Properties"
msgstr "Lastnosti oznak"
@ -14489,12 +14489,12 @@ msgstr "Hierarhične lastnosti nalepke"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Lastnosti hierarhičnega priključka"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Ime omrežja ne sme biti prazno."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -14502,12 +14502,12 @@ msgstr "Ime omrežja ne sme biti prazno."
msgid "untitled"
msgstr "Naslov:"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Lastnosti oznak"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "Prva %d polja so obvezna."
@ -45096,18 +45096,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -45116,7 +45116,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -45124,12 +45124,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -45137,7 +45137,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -45145,7 +45145,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -45154,21 +45154,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -45176,14 +45176,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -45198,7 +45198,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -45207,13 +45207,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -45222,71 +45222,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -45653,18 +45634,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/sr.po
View File

@ -5,7 +5,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-30 21:02+0000\n"
"Last-Translator: Luka Borkovic <borkovic@gmail.com>\n"
"Language-Team: Serbian <https://hosted.weblate.org/projects/kicad/v9/sr/>\n"
@ -12791,7 +12791,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Попуњавање зона"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13296,7 +13296,7 @@ msgid "Hierarchical Label Properties"
msgstr "Попуњавање зона"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
#, fuzzy
msgid "Label Properties"
msgstr "Својства круга"
@ -13311,12 +13311,12 @@ msgstr "Својства материјала"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Попуњавање зона"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Попуњавање зона"
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
@ -13324,12 +13324,12 @@ msgstr "Попуњавање зона"
msgid "untitled"
msgstr "Додај"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Својства круга"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
#, fuzzy
msgid "The first field is mandatory."
msgstr "Првих %d поља су обавезна."
@ -41724,18 +41724,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41744,7 +41744,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41752,12 +41752,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41765,7 +41765,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41773,7 +41773,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41782,21 +41782,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41804,14 +41804,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41826,7 +41826,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41835,13 +41835,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41850,71 +41850,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42281,18 +42262,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/sv.po
View File

@ -12,7 +12,7 @@ msgid ""
msgstr ""
"Project-Id-Version: \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-06 13:55+0000\n"
"Last-Translator: Johan Heikkilä <johan.heikkila@gmail.com>\n"
"Language-Team: Swedish <https://hosted.weblate.org/projects/kicad/v9/sv/>\n"
@ -12342,7 +12342,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Arkets filnamn kan bara modifieras i dialogrutan för arkegenskaper."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12796,7 +12796,7 @@ msgid "Hierarchical Label Properties"
msgstr "Egenskaper för hierarkiska etiketter"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Egenskaper för etiketter"
@ -12808,22 +12808,22 @@ msgstr "Egenskaper för direktivetiketter"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Egenskaper för hierarkiska arks stift"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Etikett kan inte vara tom."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "namnlös"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Redigera egenskaper för etiketter"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Det första fältet är obligatoriskt."
@ -39857,18 +39857,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39877,7 +39877,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39885,12 +39885,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39898,7 +39898,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39906,7 +39906,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39915,21 +39915,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39937,14 +39937,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39959,7 +39959,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39968,13 +39968,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39983,71 +39983,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41069,18 +41050,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Fler exempel\n"
"\n"

97
translation/pofiles/ta.po
View File

@ -4,7 +4,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-29 02:37+0000\n"
"Last-Translator: தமிழ்நேரம் <anishprabu.t@gmail.com>\n"
"Language-Team: Tamil <https://hosted.weblate.org/projects/kicad/v9/ta/>\n"
@ -12249,7 +12249,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "தாள் கோப்பு பெயரை தாள் பண்புகள் உரையாடலில் மட்டுமே மாற்ற முடியும்."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12703,7 +12703,7 @@ msgid "Hierarchical Label Properties"
msgstr "படிநிலை சிட்டை பண்புகள்"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "சிட்டை பண்புகள்"
@ -12715,22 +12715,22 @@ msgstr "டைரெக்டிவ் சிட்டை பண்புகள
msgid "Hierarchical Sheet Pin Properties"
msgstr "படிநிலை தாள் முள் பண்புகள்"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "சிட்டை காலியாக இருக்க முடியாது."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "தலைப்பிடப்படாத"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "சிட்டை பண்புகளைத் திருத்தவும்"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "முதல் புலம் கட்டாயமாகும்."
@ -39591,24 +39591,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39617,7 +39618,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39625,12 +39626,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39638,7 +39639,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39646,7 +39647,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39655,21 +39656,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39677,14 +39678,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39699,7 +39700,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39708,13 +39709,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39723,71 +39724,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40285,6 +40267,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -40428,18 +40411,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### மேலும் எடுத்துக்காட்டுகள்\n"
"\n"

95
translation/pofiles/th.po
View File

@ -6,7 +6,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-01-23 15:38+0000\n"
"Last-Translator: John Beard <john.j.beard@gmail.com>\n"
"Language-Team: Thai <https://hosted.weblate.org/projects/kicad/master-source/"
@ -12649,7 +12649,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "ชื่อไฟล์ของแผ่นชีตสามารถเปลี่ยนได้ในกรอบสนทนาคุณสมบัติแผ่นชีตเท่านั้น"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -13114,7 +13114,7 @@ msgid "Hierarchical Label Properties"
msgstr "คุณสมบัติป้ายชื่อลำดับขั้น"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "คุณสมบัติป้ายชื่อ"
@ -13126,23 +13126,23 @@ msgstr "คุณสมบัติป้ายชื่อคำสั่ง"
msgid "Hierarchical Sheet Pin Properties"
msgstr "คุณสมบัติขาชีทชนิดลำดับขั้น"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "ป้ายชื่อว่างไม่ได้"
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "ไม่มีชื่อ"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "คุณสมบัติป้ายชื่อ"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "ฟิลด์แรกเป็นฟิลด์บังคับ"
@ -40721,18 +40721,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40741,7 +40741,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40749,12 +40749,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40762,7 +40762,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40770,7 +40770,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40779,21 +40779,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40801,14 +40801,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40823,7 +40823,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40832,13 +40832,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40847,71 +40847,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41278,18 +41259,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

105
translation/pofiles/tr.po
View File

@ -23,7 +23,7 @@ msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-07-06 13:55+0000\n"
"Last-Translator: YÜKSEL AÇIKGÖZ <yukselacikgoz@gmail.com>\n"
"Language-Team: Turkish <https://hosted.weblate.org/projects/kicad/v9/tr/>\n"
@ -12316,7 +12316,7 @@ msgstr ""
"değiştirilebilir."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12771,7 +12771,7 @@ msgid "Hierarchical Label Properties"
msgstr "Hiyerarşik Etiket Özellikleri"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Etiket Özellikleri"
@ -12783,22 +12783,22 @@ msgstr "Yönerge Etiket Özellikleri"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Hiyerarşik Sayfa Pin Özellikleri"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Etiket boş olamaz."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "başlıksız"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "Etiket Özelliklerini Düzenle"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "İlk alan zorunludur."
@ -13554,8 +13554,8 @@ msgid ""
"in the schematic.\n"
"Do you wish to continue?"
msgstr ""
"Bu pin %d mil ızgarada değil, bu da şemada bağlantı kurmayı zorlaştıracaktır."
"\n"
"Bu pin %d mil ızgarada değil, bu da şemada bağlantı kurmayı "
"zorlaştıracaktır.\n"
"Devam etmek ister misiniz?"
#: eeschema/dialogs/dialog_pin_properties.cpp:452
@ -38567,8 +38567,8 @@ msgstr "Döndürme komutları için adım:"
#: pcbnew/dialogs/panel_edit_options_base.cpp:44
msgid "Set increment (in degrees) for context menu and hotkey rotation."
msgstr ""
"Bağlam menüsü ve kısayol tuşu döndürme için artırma miktarını (derece olarak)"
" ayarla."
"Bağlam menüsü ve kısayol tuşu döndürme için artırma miktarını (derece "
"olarak) ayarla."
#: pcbnew/dialogs/panel_edit_options_base.cpp:56
msgid "Arc editing mode:"
@ -39790,24 +39790,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39816,7 +39817,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39824,12 +39825,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39837,7 +39838,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39845,7 +39846,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39854,21 +39855,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39876,14 +39877,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39898,7 +39899,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39907,13 +39908,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39922,71 +39923,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40592,6 +40574,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -40735,18 +40718,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### Daha Fazla Örnek\n"
"\n"

95
translation/pofiles/uk.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-05-10 13:03+0000\n"
"Last-Translator: Ivan Chuba <xtrvweb@gmail.com>\n"
"Language-Team: Ukrainian <https://hosted.weblate.org/projects/kicad/v9/uk/>\n"
@ -12495,7 +12495,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "Ім'я файлу листа можна змінити лише в діалозі властивостей листа."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12962,7 +12962,7 @@ msgid "Hierarchical Label Properties"
msgstr "Властивості ієрархічної мітки"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Властивості мітки"
@ -12974,23 +12974,23 @@ msgstr "Властивості директивної мітки"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Властивості виводу ієрархічного аркуша"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "Мітка не може бути незаповненою."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "без назви"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Властивості мітки"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Перше поле є обов'язковим."
@ -40712,18 +40712,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -40732,7 +40732,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -40740,12 +40740,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -40753,7 +40753,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -40761,7 +40761,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -40770,21 +40770,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -40792,14 +40792,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -40814,7 +40814,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -40823,13 +40823,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -40838,71 +40838,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -41269,18 +41250,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

95
translation/pofiles/vi.po
View File

@ -10,7 +10,7 @@ msgid ""
msgstr ""
"Project-Id-Version: Kicad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-02-10 23:20+0000\n"
"Last-Translator: Seth Hillbrand <seth@kipro-pcb.com>\n"
"Language-Team: Vietnamese <https://hosted.weblate.org/projects/kicad/master-"
@ -12723,7 +12723,7 @@ msgstr ""
"Tên tệp trang vẽ chỉ có thể được sửa đổi trong hộp thoại Thuộc tính Trang vẽ."
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
#, fuzzy
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
@ -13210,7 +13210,7 @@ msgid "Hierarchical Label Properties"
msgstr "Thuộc tính nhãn phân cấp"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "Thuộc tính nhãn"
@ -13224,24 +13224,24 @@ msgstr "Thuộc tính nhãn phân cấp"
msgid "Hierarchical Sheet Pin Properties"
msgstr "Thuộc tính ghim bảng phân cấp"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
#, fuzzy
msgid "Label can not be empty."
msgstr "Giá trị không được để trống."
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr ""
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
#, fuzzy
msgid "Edit Label Properties"
msgstr "Thuộc tính nhãn"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "Trường đầu tiên là bắt buộc."
@ -41540,18 +41540,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -41560,7 +41560,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -41568,12 +41568,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -41581,7 +41581,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -41589,7 +41589,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -41598,21 +41598,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -41620,14 +41620,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -41642,7 +41642,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -41651,13 +41651,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -41666,71 +41666,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -42097,18 +42078,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19

97
translation/pofiles/zh_CN.po
View File

@ -40,7 +40,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-29 11:25+0000\n"
"Last-Translator: CloverGit <w991593239@163.com>\n"
"Language-Team: Chinese (Simplified Han script) <https://hosted.weblate.org/"
@ -12158,7 +12158,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "图纸文件名只能在图纸属性对话框中修改。"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12610,7 +12610,7 @@ msgid "Hierarchical Label Properties"
msgstr "层次标签属性"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "标签属性"
@ -12622,22 +12622,22 @@ msgstr "指令标签属性"
msgid "Hierarchical Sheet Pin Properties"
msgstr "层次图纸引脚属性"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "标签不能为空。"
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "无标题"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "编辑标签属性"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "首字段是必填项。"
@ -39016,24 +39016,25 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_2constraints.h:2
#, fuzzy
msgid ""
"### Constraints\n"
"\n"
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39042,7 +39043,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39050,12 +39051,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39063,7 +39064,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39071,7 +39072,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39080,21 +39081,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39102,14 +39103,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39124,7 +39125,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39133,13 +39134,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39148,71 +39149,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -39810,6 +39792,7 @@ msgstr ""
"\n"
#: pcbnew/dialogs/panel_setup_rules_help_9more_examples.h:2
#, fuzzy
msgid ""
"### More Examples\n"
"\n"
@ -39953,18 +39936,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
"### 更多示例\n"
"\n"

95
translation/pofiles/zh_TW.po
View File

@ -18,7 +18,7 @@ msgid ""
msgstr ""
"Project-Id-Version: KiCad\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2025-07-03 20:16+0300\n"
"POT-Creation-Date: 2025-07-07 17:43+0300\n"
"PO-Revision-Date: 2025-06-27 06:02+0000\n"
"Last-Translator: pominglee <pominglee@gmail.com>\n"
"Language-Team: Chinese (Traditional Han script) <https://hosted.weblate.org/"
@ -12186,7 +12186,7 @@ msgid "Sheet filename can only be modified in Sheet Properties dialog."
msgstr "圖紙檔案名只能在圖紙屬性對話框中修改。"
#: eeschema/dialogs/dialog_field_properties.cpp:626
#: eeschema/dialogs/dialog_label_properties.cpp:520
#: eeschema/dialogs/dialog_label_properties.cpp:532
msgid ""
"Intersheet reference visibility is controlled globally from Schematic Setup "
"> General > Formatting"
@ -12638,7 +12638,7 @@ msgid "Hierarchical Label Properties"
msgstr "層次標籤屬性"
#: eeschema/dialogs/dialog_label_properties.cpp:140
#: eeschema/dialogs/dialog_label_properties_base.h:123
#: eeschema/dialogs/dialog_label_properties_base.h:124
msgid "Label Properties"
msgstr "標籤屬性"
@ -12650,22 +12650,22 @@ msgstr "指令標籤屬性"
msgid "Hierarchical Sheet Pin Properties"
msgstr "層次圖紙接腳屬性"
#: eeschema/dialogs/dialog_label_properties.cpp:500
#: eeschema/dialogs/dialog_label_properties.cpp:512
msgid "Label can not be empty."
msgstr "標籤不能為空。"
#: eeschema/dialogs/dialog_label_properties.cpp:564
#: eeschema/dialogs/dialog_label_properties.cpp:576
#: eeschema/dialogs/dialog_lib_symbol_properties.cpp:443
#: eeschema/dialogs/dialog_sheet_properties.cpp:397
#: eeschema/dialogs/dialog_symbol_properties.cpp:743 include/project.h:43
msgid "untitled"
msgstr "無標題"
#: eeschema/dialogs/dialog_label_properties.cpp:640
#: eeschema/dialogs/dialog_label_properties.cpp:652
msgid "Edit Label Properties"
msgstr "編輯標籤屬性"
#: eeschema/dialogs/dialog_label_properties.cpp:783
#: eeschema/dialogs/dialog_label_properties.cpp:795
msgid "The first field is mandatory."
msgstr "第一個欄位是必填的。"
@ -39072,18 +39072,18 @@ msgid ""
"| Constraint type | Argument "
"type "
"| "
"Description "
"Description "
"|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n"
"| `annular_width` | min/opt/"
"max "
"| Checks the width of annular rings on vias."
"<br> "
"<br> "
"|\n"
"| `assertion` | \"&lt;"
"expression>\" "
"| Checks the given expression."
"<br> "
"<br> "
"|\n"
"| `clearance` | "
"min "
@ -39092,7 +39092,7 @@ msgid ""
"objects regardless of net.)<br><br>To allow copper objects to overlap "
"(collide), create a `clearance` constraint with the `min` value less than "
"zero (for example, `-1`)."
"<br> "
"<br> "
"|\n"
"| `courtyard_clearance` | "
"min "
@ -39100,12 +39100,12 @@ msgid ""
"if any two courtyards are closer than the `min` distance. If a footprint "
"does not have a courtyard shape, no errors will be generated from this "
"constraint."
"<br> "
"<br> "
"|\n"
"| `creepage` | "
"min "
"| Specifies the creepage distance between copper objects of different nets."
"<br> "
"<br> "
"|\n"
"| `diff_pair_gap` | min/opt/"
"max "
@ -39113,7 +39113,7 @@ msgid ""
"tracks are segments that are parallel to each other. Differential pair gap "
"is not tested on uncoupled portions of a differential pair (for example, the "
"fanout from a component)."
"<br> "
"<br> "
"|\n"
"| `diff_pair_uncoupled` | "
"max "
@ -39121,7 +39121,7 @@ msgid ""
"from the other polarity track in the pair (for example, where the pair fans "
"out from a component, or becomes uncoupled to pass around another object "
"such as a via)."
"<br> "
"<br> "
"|\n"
"| `disallow` | "
"`track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> "
@ -39130,21 +39130,21 @@ msgid ""
"pad)`. If an object of this type matches the rule condition, a DRC error "
"will be created.<br><br>This constraint is essentially the same as a keepout "
"rule area, but can be used to create more specific keepout restrictions."
"<br> |\n"
"<br> |\n"
"| `edge_clearance` | min/opt/"
"max "
"| Checks the clearance between objects and the board edge.<br><br>This can "
"also be thought of as the \"milling tolerance\" as the board edge will "
"include all graphical items on the `Edge.Cuts` layer as well as any *oval* "
"pad holes. (See `physical_hole_clearance` for the drilling "
"tolerance.)<br> "
"tolerance.)<br> "
"|\n"
"| `length` | min/"
"max "
"| Checks the total routed length for the nets that match the rule condition "
"and generates an error for each net that is below the `min` value (if "
"specified) or above the `max` value (if specified) of the constraint."
"<br> "
"<br> "
"|\n"
"| `hole` | min/"
"max "
@ -39152,14 +39152,14 @@ msgid ""
"holes, the smaller (minor) diameter will be tested against the `min` value "
"(if specified) and the larger (major) diameter will be tested against the "
"`max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `hole_clearance` | "
"min "
"| Checks the clearance between a drilled hole in a pad or via and copper "
"objects on a different net. The clearance is measured from the diameter of "
"the hole, not its center."
"<br> "
"<br> "
"|\n"
"| `hole_to_hole` | "
"min "
@ -39174,7 +39174,7 @@ msgid ""
"| Checks the clearance between two objects on a given layer (including non-"
"copper layers).<br><br>While this can perform more general-purpose checks "
"than `clearance`, it is much slower. Use `clearance` where possible."
"<br> "
"<br> "
"|\n"
"| `physical_hole_clearance` | "
"min "
@ -39183,13 +39183,13 @@ msgid ""
"the hole, not its center.<br><br>This can also be thought of as the "
"\"drilling tolerance\" as it only includes **round** holes (see "
"`edge_clearance` for the milling tolerance)."
"<br> "
"<br> "
"|\n"
"| `silk_clearance` | min/opt/"
"max "
"| Checks the clearance between objects on silkscreen layers and other "
"objects."
"<br> "
"<br> "
"|\n"
"| `skew` | "
"max "
@ -39198,71 +39198,52 @@ msgid ""
"lengths of each net that is matched by the rule. If the absolute value of "
"the difference between that average and the length of any one net is above "
"the constraint `max` value, an error will be generated."
"<br> "
"|\n"
"| `solder_mask_expansion` | "
"opt "
"| Specifies the solder mask expansion for pads, shapes and "
"tracks. "
"|\n"
"| `solder_paste_abs_margin` | "
"opt "
"| Specifies the absolute solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"|\n"
"| `solder_paste_rel_margin` | "
"opt "
"| Specifies the relative solder paste clearance for pads. Usually negative "
"to inset the paste.<br><br>The final solder paste clearace will be the "
"absolute clearance plus the relative "
"clearance. "
"<br> "
"|\n"
"| `thermal_relief_gap` | "
"min "
"| Specifies the width of the gap between a pad and a zone with a thermal-"
"relief connection."
"<br> "
"<br> "
"|\n"
"| `thermal_spoke_width` | "
"opt "
"| Specifies the width of the spokes connecting a pad to a zone with a "
"thermal-relief connection."
"<br> "
"<br> "
"|\n"
"| `track_width` | min/opt/"
"max "
"| Checks the width of track and arc segments. An error will be generated "
"for each segment that has a width below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_angle` | min/opt/"
"max "
"| Checks the angle between two connected track segments. An error will be "
"generated for each connected pair with an angle below the `min` value (if "
"specified) or above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `track_segment_length` | min/"
"max "
"| Checks the length of track and arc segments. An error will be generated "
"for each segment that has a length below the `min` value (if specified) or "
"above the `max` value (if specified)."
"<br> "
"<br> "
"|\n"
"| `via_count` | "
"max "
"| Counts the number of vias on every net matched by the rule condition. If "
"that number exceeds the constraint `max` value on any matched net, an error "
"will be generated for that net."
"<br> "
"<br> "
"|\n"
"| `zone_connection` | "
"`solid`<br>`thermal_reliefs`<br>`none` "
"| Specifies the connection to be made between a zone and a pad."
"<br> "
"<br> "
"|\n"
"\n"
"\n"
@ -40112,18 +40093,6 @@ msgid ""
" (constraint hole_to_hole)\n"
" (severity ignore))\n"
"\n"
"\n"
" # No solder mask expansion for vias.\n"
" (rule \"no mask expansion on vias\"\n"
" (constraint solder_mask_expansion (opt 0mm))\n"
" (condition \"A.type == via\"))\n"
"\n"
"\n"
" # Remove solder paste from DNP footprints.\n"
" (rule remove_solder_paste_from_DNP\n"
" (constraint solder_paste_abs_margin (opt -50mm))\n"
" (condition \"A.Do_not_Populate\"))\n"
"\n"
msgstr ""
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19