realAscot/kicad-source
1
0
Fork 0
mirror of https://gitlab.com/kicad/code/kicad.git synced 2025-09-14 10:13:19 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add some checkpoints to qa_pcbnew

Browse Source
This commit is contained in:
Marek Roszko 2025-06-07 15:02:52 -04:00
parent a5e4ed38a3
commit 4ada004bb4
2 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
qa/pcbnew_utils/board_test_utils.cpp
View File

@ -106,21 +106,31 @@ void LoadBoard( SETTINGS_MANAGER& aSettingsManager, const wxString& aRelPath,
auto m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard.get(), &aBoard->GetDesignSettings() ); auto m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard.get(), &aBoard->GetDesignSettings() );
BOOST_TEST_CHECKPOINT( "Init drc engine" );
if( rulesFile.Exists() ) if( rulesFile.Exists() )
m_DRCEngine->InitEngine( rulesFile ); m_DRCEngine->InitEngine( rulesFile );
else else
m_DRCEngine->InitEngine( wxFileName() ); m_DRCEngine->InitEngine( wxFileName() );
aBoard->GetDesignSettings().m_DRCEngine = m_DRCEngine; aBoard->GetDesignSettings().m_DRCEngine = m_DRCEngine;
BOOST_TEST_CHECKPOINT( "Build list of nets" );
aBoard->BuildListOfNets(); aBoard->BuildListOfNets();
BOOST_TEST_CHECKPOINT( "Build connectivity" );
aBoard->BuildConnectivity(); aBoard->BuildConnectivity();
BOOST_TEST_CHECKPOINT( "Synchronize Time Domain Properties" );
aBoard->GetLengthCalculation()->SynchronizeTimeDomainProperties(); aBoard->GetLengthCalculation()->SynchronizeTimeDomainProperties();
if( aBoard->GetProject() ) if( aBoard->GetProject() )
{ {
std::unordered_set<wxString> dummy; std::unordered_set<wxString> dummy;
BOOST_TEST_CHECKPOINT( "Synchronize Component Classes" );
aBoard->SynchronizeComponentClasses( dummy ); aBoard->SynchronizeComponentClasses( dummy );
BOOST_TEST_CHECKPOINT( "Run DRC cache generator" );
DRC_CACHE_GENERATOR cacheGenerator; DRC_CACHE_GENERATOR cacheGenerator;
cacheGenerator.SetDRCEngine( m_DRCEngine.get() ); cacheGenerator.SetDRCEngine( m_DRCEngine.get() );
cacheGenerator.Run(); cacheGenerator.Run();
@ -275,6 +285,8 @@ void LoadAndTestFootprintFile( const wxString& aLibRelativePath, const wxString&
void FillZones( BOARD* m_board ) void FillZones( BOARD* m_board )
{ {
BOOST_TEST_CHECKPOINT( "Filling zones" );
TOOL_MANAGER toolMgr; TOOL_MANAGER toolMgr;
toolMgr.SetEnvironment( m_board, nullptr, nullptr, nullptr, nullptr ); toolMgr.SetEnvironment( m_board, nullptr, nullptr, nullptr, nullptr );
@ -291,6 +303,7 @@ void FillZones( BOARD* m_board )
if( filler.Fill( toFill, false, nullptr ) ) if( filler.Fill( toFill, false, nullptr ) )
commit.Push( _( "Fill Zone(s)" ), SKIP_UNDO | SKIP_SET_DIRTY | ZONE_FILL_OP | SKIP_CONNECTIVITY ); commit.Push( _( "Fill Zone(s)" ), SKIP_UNDO | SKIP_SET_DIRTY | ZONE_FILL_OP | SKIP_CONNECTIVITY );
BOOST_TEST_CHECKPOINT( "Building connectivity (after zone fill)" );
m_board->BuildConnectivity(); m_board->BuildConnectivity();
} }

1
qa/tests/pcbnew/drc/test_drc_copper_sliver.cpp
View File

@ -85,6 +85,7 @@ BOOST_DATA_TEST_CASE_F( DRC_REGRESSION_TEST_FIXTURE, DRCCopperSliver,
violations.push_back( *aItem ); violations.push_back( *aItem );
} ); } );
BOOST_TEST_CHECKPOINT( "Running copper sliver drc" );
bds.m_DRCEngine->RunTests( EDA_UNITS::MM, true, false ); bds.m_DRCEngine->RunTests( EDA_UNITS::MM, true, false );
if( violations.size() == test.second ) if( violations.size() == test.second )