diff --git a/common/pcb.keywords b/common/pcb.keywords
index a889be2e2e..4b49169ab6 100644
--- a/common/pcb.keywords
+++ b/common/pcb.keywords
@@ -150,6 +150,7 @@ mod_text_width
 mode
 model
 module
+name
 net
 net_class
 net_name
diff --git a/pcbnew/class_zone.cpp b/pcbnew/class_zone.cpp
index 602764fa79..b93ec0e3c9 100644
--- a/pcbnew/class_zone.cpp
+++ b/pcbnew/class_zone.cpp
@@ -639,11 +639,14 @@ void ZONE_CONTAINER::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PA
 
         // Display priority level
         msg.Printf( wxT( "%d" ), GetPriority() );
-        aList.emplace_back( _( "Priority" ), msg, BLUE  );
+        aList.emplace_back( _( "Priority" ), msg, BLUE );
     }
 
     aList.emplace_back( _( "Layer" ), LayerMaskDescribe( GetBoard(), m_layerSet ), DARKGREEN );
 
+    if( !m_zoneName.empty() )
+        aList.emplace_back( _( "Name" ), m_zoneName, DARKMAGENTA );
+
     switch( m_FillMode )
     {
     case ZONE_FILL_MODE::POLYGONS:      msg = _( "Solid" ); break;
diff --git a/pcbnew/class_zone.h b/pcbnew/class_zone.h
index 6ab8009130..609092be2f 100644
--- a/pcbnew/class_zone.h
+++ b/pcbnew/class_zone.h
@@ -105,6 +105,10 @@ public:
 
     virtual LSET GetLayerSet() const override;
 
+    wxString GetZoneName() const { return m_zoneName; }
+
+    void SetZoneName( const wxString& aName ) { m_zoneName = aName; }
+
     /** Function GetBoundingBox (virtual)
      * @return an EDA_RECT that is the bounding box of the zone outline
      */
@@ -763,6 +767,9 @@ protected:
     int                   m_cornerSmoothingType;
     unsigned int          m_cornerRadius;
 
+    /// An optional unique name for this zone, used for identifying it in DRC checking
+    wxString              m_zoneName;
+
     LSET                  m_layerSet;
 
     /* Priority: when a zone outline is inside and other zone, if its priority is higher
diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp
index 5a1bc87e18..814a7c11d5 100644
--- a/pcbnew/kicad_plugin.cpp
+++ b/pcbnew/kicad_plugin.cpp
@@ -1792,6 +1792,9 @@ void PCB_IO::format( ZONE_CONTAINER* aZone, int aNestLevel ) const
 
     m_out->Print( 0, " (tstamp %s)", TO_UTF8( aZone->m_Uuid.AsString() ) );
 
+    if( !aZone->GetZoneName().empty() )
+        m_out->Print( 0, " (name %s)", TO_UTF8( aZone->GetZoneName() ) );
+
     // Save the outline aux info
     std::string hatch;
 
diff --git a/pcbnew/kicad_plugin.h b/pcbnew/kicad_plugin.h
index 386150fd71..9ac1919e11 100644
--- a/pcbnew/kicad_plugin.h
+++ b/pcbnew/kicad_plugin.h
@@ -69,7 +69,8 @@ class TEXTE_PCB;
 //#define SEXPR_BOARD_FILE_VERSION    20200119  // arcs in tracks
 //#define SEXPR_BOARD_FILE_VERSION    20200512  // page -> paper
 //#define SEXPR_BOARD_FILE_VERSION    20200518  // save hole_to_hole_min
-#define SEXPR_BOARD_FILE_VERSION      20200614  // Add support for fp_rects and gr_rects
+//#define SEXPR_BOARD_FILE_VERSION    20200614  // Add support for fp_rects and gr_rects
+#define SEXPR_BOARD_FILE_VERSION      20200623  // Add name property to zones
 
 #define CTL_STD_LAYER_NAMES         (1 << 0)    ///< Use English Standard layer names
 #define CTL_OMIT_NETS               (1 << 1)    ///< Omit pads net names (useless in library)
diff --git a/pcbnew/pcb_parser.cpp b/pcbnew/pcb_parser.cpp
index 472d0739ed..341bb5f403 100644
--- a/pcbnew/pcb_parser.cpp
+++ b/pcbnew/pcb_parser.cpp
@@ -4106,9 +4106,17 @@ ZONE_CONTAINER* PCB_PARSER::parseZONE_CONTAINER( BOARD_ITEM_CONTAINER* aParent )
             }
             break;
 
+        case T_name:
+            {
+                NextTok();
+                zone->SetZoneName( FromUTF8() );
+                NeedRIGHT();
+            }
+            break;
+
         default:
             Expecting( "net, layer/layers, tstamp, hatch, priority, connect_pads, min_thickness, "
-                       "fill, polygon, filled_polygon, or fill_segments" );
+                       "fill, polygon, filled_polygon, fill_segments or name" );
         }
     }